1.3.5. External processor bus

The test chip on the CT-R4F has two external AXI bus interfaces, one master and one slave. The test chip AXI Slave port is available at the HDRY header and the AXI Master port is available at the HDRX header. See Header connectors for a listing of the AXI signals on the HDRX and HDRY headers and Bus interface characteristics for parametric data.

Copyright © 2009-2011 ARM Limited. All rights reserved.ARM DUI 0441C
Non-ConfidentialID021412