3.3.1. Test chip PLLs

A simplified diagram of the PLL design in the ARM Cortex-R4F test chip is shown in Figure 3.3.

Figure 3.3. ARM Cortex-R4F test chip PLL

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The PLLs are configured by the CT-R4F PLD using the Serial Configuration Controller (SCC) in the test chip.

The M divider shown in Figure 3.3Figure 3.3 follows a binary divide ratio mapping, as shown in Table 3.1.

Table 3.1. M binary divide ratio

M[3]M[2]M[1]M[0]Divide ratio
000016
00011
00102
..........
111115

The N divider shown in Figure 3.3 follows a binary divide ratio mapping, as shown in Table 3.2.

Table 3.2. N binary divide ratio

N[2]N[1]N[0]Divide ratio
0008
0011
0102
........
1117

The frequency of CLKOUT is obtained by the following formula:

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The frequency of the Voltage Controlled Oscillator (VCO) (Fvco) is obtained by adjusting the parameters for each of the three PLLs. This is described by the following formulas:

The absolute range limits for counter values are:

Table 3.3 shows the absolute range limits for the PLL frequency.

Table 3.3. Absolute range limits for PLL frequency

FrequencySymbolMinimumMaximumUnit
REFCLKFREFCLK33300MHz
VCOFVCO133533MHz
CLKOUTFCLKOUT33533MHz

See also CT-R4F configuration.

Note

Default values are provided by the EB during reset. If you want to change these default values you are advised to contact ARM Support for assistance as not all combinations of values are always supported.

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