3.10.3. CoreSight sub-system

A simplified diagram of the CoreSight sub-system is shown in Figure 3.11. Each of the system elements is listed and briefly described in Table 3.11. For information on CoreSight, see CoreSight Technology System Design Guide (ARM DGI 0012) and for information on the individual CoreSight components, see CoreSight Components Technical Reference Manual (ARM DDI 0314).

Figure 3.11. CoreSight sub-system

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The DAP ROM in the ARM Cortex-R4F test chip is not operational. For information on setting up RVI for use with the Debug APB see Application Note 217 Using a CT-R4F with the RealView Emulation Baseboard supplied on the Versatile CD or visit the FAQ section of the ARM website.

Table 3.11. CoreSight components

CoreSight ComponentBase Address REMAP = 000 REMAP = 010Base Address REMAP = 001 REMAP = 100Description
CTI CPU_ETM)0xE00290000xD0029000Cross Trigger Interface, part of the Embedded Cross Trigger (ECT). See CoreSight Components Technical Reference Manual (ARM DDI 0314) for details.
ETM-R40xE00280000xD0028000Embedded Trace MacroCell, provides instruction trace and data trace for the ARM Cortex-R4F processor. See CoreSight ETM-R4 Technical Reference Manual (ARM DDI 0367) for further details.
R4F _APB0xE00270000xD0027000The ARM Cortex-R4F processor debug unit APB slave port. See Cortex-R4 and Cortex-R4F Technical Reference Manual (ARM DDI 0363) for details.
SWD0xE00260000xD0026000Serial Wire Debug unit, part of the Debug Access Port (DAP).
ITM0xE00250000xD0025000Instrumentation Trace Macrocell, with supporting code, generates SoftWare Instrumentation Trace (SWIT).
Funnel0xE00240000xD0024000CoreSight Trace Funnel, used when there is more than one trace source. The CSTF combines multiple trace streams into a single AMBA Trace Bus (ATB).
TPIU0xE00230000xD0023000Trace Port Interface Unit, acts as a bridge between the on-chip trace data and the data stream captured by the external Trace Port Analyzer (TPA).
CTI (CoreSight sub-system)0xE00220000xD0022000Cross Trigger Interface, part of the Embedded Cross Trigger (ECT). See CoreSight Components Technical Reference Manual (ARM DDI 0314) for details.
ETB0xE00210000xD0021000Embedded Trace Buffer, provides on-chip storage of trace data using 32-bit RAM.
DAP_ROM0xE00200000xD0020000Internal ROM table, stores the locations of the components on the Debug APB.
ReplicatorATB replicator, sends identical trace data from an incoming ATB slave port interface to two outgoing ATB master port interfaces.

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