4.2.3. CT-R4F Oscillator configuration

There are three ICS307 programmable oscillators on the CT-R4F and one fixed 24MHz oscillator. The 24MHz oscillator is the reference clock, TIMCLK for the timer in the ARM Cortex-R4F test chip. See ARM Dual-Timer Module (SP804) Technical Reference Manual (ARM DDI 0271) for details.

Note

The default clock frequencies are determined at reset by the EB sending programming information to the CT-R4F. Suitable default values are not specified by the CT-R4F itself. If a custom baseboard is used, it is a requirement that the custom baseboard provides suitable default values. See ARM Cortex-R4F test chip configuration at reset for programming details.

The programmable oscillators are:

OSC0

The reference clock (REFCLK) for the test chip PLL (PLL0) that generates CPU_CLK.

For default frequency REFCLK = 50MHz and default CLOCK_MODE = b01:

  • CPU_CLK = 250MHz

  • ACLK = 125MHz

  • PCLK = 15.625MHz

OSC1

The reference clock (FBCLK_IN) for the test chip PLL (PLL1) that generates MCLK.

For default frequency 67MHz: FBCLK_IN = SDRAM_CLK = MCLK = 134MHz (OSC1 x2).

OSC2

The reference clock for the test chip CLCD controller (PL111).

For default frequency = 25MHz: CLCDCLK_IO = 25MHz.

See Clocks for details of the clock routing on the CT-R4F and within the ARM Cortex-R4F test chip.

Setting the programmable oscillator frequency

The output frequencies of the ICS307 programmable oscillators are controlled by divider values loaded into the serial data input pins on the oscillators. The divider values required are transferred during reset from the CT_R4F_OSCx registers in the CT-R4F PLD. The CT_R4F_OSCx registers are accessed via the CT-R4F 4-wire serial interface. See Overview of Core Tile configuration for details of the 4-wire serial interface address and data stream format, and Table 4.10 for the location of all the CT_R4F_OSCx registers.

You can calculate the oscillator output frequency from the formula:

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where:

VDW

Is the VCO divider word (4 - 511) read from CT_R4F_OSCx[8:0]

RDW

Is the reference divider word (1 - 127) read from CT_R4F_OSCx[15:9]

OD

Is the output divider select (2 to 10) read from CT_R4F_OSCx[18:16]:

  • b000 selects divide by 10

  • b001 selects divide by 2

  • b010 selects divide by 8

  • b011 selects divide by 4

  • b100 selects divide by 5

  • b101 selects divide by 7

  • b110 selects divide by 3

  • b111 selects divide by 6.

For more information on the ICS clock generator and a frequency calculator, see the IDT web site: www.idt.com.

CT_R4F_OSC registers

Figure 4.7 shows the bit allocations within each register.

Figure 4.7. CT_R4F_OSC register

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The CT_R4F_OSC registers hold the values that set the OSC[0:2] reference clock frequencies. The registers are accessed using the 4-wire serial interface to the CT-R4F PLD. The function of the register bits are listed in Table 4.17.

Table 4.17. CT_R4F_OSC register bit assignments

BitsAccessNameDescription
[31:20]Write ignored, Read as zeroReserved
[19]Write ignored, Read as zeroReserved
[18:16]WriteODOutput Divider value
[15:9]WriteRDWReference Divider Word value
[8:0]WriteVDWVCO Divider word value

The serial stream address, the default divider values sent by the EB, and the resulting frequency of each reference oscillator are listed in Table 4.18.

Table 4.18. CT_R4F_OSC register default values

CT_R4F_OSC registerSerial stream addressOD dividerRDW dividerVDW dividerFrequency
CT_R4F_OSC00x1004b011b0010110b00101110050MHz
CT_R4F_OSC10x1005b011b0010110b00111111067MHz
CT_R4F_OSC20x1006b000b0010110b00111010125MHz

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