5.4.1. Core Tile timing and the AMBA 3 AXI Protocol

The worst case timing figures at the CT-R4F headers are shown in Table 5.8 and Table 5.9. You must use these figures as a guideline when designing your own boards.

The system bus on RealView Logic Tiles and baseboards is routed between FPGAs. The exact performance of a system depends on the timing parameters of the baseboard and all tiles in the system. Some allowance also has to be made for clock skew, routing delays and number of modules (that is, loading).

Not all Logic Tile or baseboard FPGA implementations meet the ideal timing parameters, because of the complexity of the design or routing congestion within the device. For this reason, the PLL clock generators on baseboards default to a safe low value that all modules can achieve. See the documentation supplied with your baseboard for details on changing the clock frequency.

A detailed timing analysis involves calculating the input/output delays between modules for all timing parameters. In general, the simplest approach to determine the maximum operating frequency is to increase the frequency of the clock generators until the system becomes unstable.

AXI Clock

The AMBA 3 AXI protocol includes a single clock signal, ACLK. All input signals are sampled on the rising edge of ACLK. All output signal changes must occur after the rising edge of ACLK.

There must be no combinatorial paths between input and output signals on both master and slave interfaces.

The ARM Cortex-R4F test chip has two external clocks:


This clock drives the test chip AXI ports signal multiplexers and is exported at the HDRZ header as CLK_OUT_MINUS1.


This clock drives the pad side of the test chip AXI matrix and is exported to the HDRZ header as CLK_NEG_DN_OUT.

AXI Reset

The AMBA 3 AXI protocol includes a single active LOW reset signal, ARESETn. The reset signal can be asserted asynchronously, but de-assertion must be synchronous after the rising edge of ACLK.


nSYSPOR is the CT-R4F global AXI reset (ARESETn).

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