Core Tile for ARM® Cortex™-R4F User Guide


Table of Contents

About this book
Intended audience
Using this book
Typographical conventions
Other conventions
Further reading
Feedback on this document
Feedback on the ARM Core Tiles
1. Introduction
1.1. Precautions
1.1.1. Ensuring safety
1.1.2. Preventing damage
1.2. About Core Tiles
1.3. Overview of CT-R4F
1.3.1. System architecture
1.3.2. External logic
1.3.3. ARM Cortex-R4F test chip
1.3.4. CT-R4F configuration
1.3.5. External processor bus
1.3.6. Memory
1.3.7. Video interface
1.3.8. Clock generation
1.3.9. JTAG
1.3.10. Power supply monitoring
1.3.11. Configuration switches
1.3.12. LED indicators
2. Getting Started
2.1. Using the CT-R4F with an Emulation Baseboard
2.2. Connecting power
2.2.1. Supplying power to the EB
2.3. Connecting JTAG debugging equipment
2.3.1. CoreSight Serial Wire Debug
2.3.2. Connecting a JTAG device to the EB
2.3.3. Connecting Trace
2.4. Using the CT-R4F with a custom baseboard
3. CT-R4F Hardware Description
3.1. Core Tile architecture
3.2. ARM Cortex-R4F test chip
3.3. Clocks
3.3.1. Test chip PLLs
3.4. Resets and interrupts
3.4.1. Resets
3.4.2. CT-R4F reset sequencing
3.4.3. Interrupts
3.5. DVI and CLCD routing
3.6. Power supply monitoring
3.7. AXI bus multiplexing
3.7.1. Multiplexing scheme
3.8. Overview of Core Tile configuration
3.8.1. CT-R4F PLD signals
3.9. Memory system
3.9.1. Memory Remap
3.10. JTAG support
3.10.1. JTAG debug scan chain routing
3.10.2. JTAG configuration scan chain routing
3.10.3. CoreSight sub-system
4. Programmer’s Reference
4.1. Memory maps
4.1.1. Peripheral memory maps
4.2. CT-R4F configuration
4.2.1. ARM Cortex-R4F test chip configuration at reset
4.2.2. ARM Cortex-R4F test chip configuration after reset
4.2.3. CT-R4F Oscillator configuration
4.2.4. DVI and CLCD configuration
4.3. Board level control and status
4.3.1. CT_R4F_CTRL register
4.4. Power supply monitoring
4.4.1. CT_R4F_ADC registers
4.5. Board identification
4.5.1. CT-R4F ID register
5. Signal Descriptions
5.1. Header connectors
5.1.1. HDRX signals
5.1.2. HDRY signals
5.1.3. HDRZ signals
5.2. CLCD DVI display interface
5.3. Trace connectors
5.4. AXI bus timing specification
5.4.1. Core Tile timing and the AMBA 3 AXI Protocol
5.4.2. Timing parameters
A. Specifications
A.1. Electrical specification
A.1.1. Bus interface characteristics
A.1.2. Current requirements
A.2. Mechanical details

Proprietary Notice

Words and logos marked with ® or ™ are registered trademarks or trademarks of ARM® Limited in the EU and other countries, except as otherwise stated below in this proprietary notice. Other brands and names mentioned herein may be the trademarks of their respective owners.

Neither the whole nor any part of the information contained in, or the product described in, this document may be adapted or reproduced in any material form except with the prior written permission of the copyright holder.

The product described in this document is subject to continuous developments and improvements. All particulars of the product and its use contained in this document are given by ARM Limited in good faith. However, all warranties implied or expressed, including but not limited to implied warranties of merchantability, or fitness for purpose, are excluded.

This document is intended only to assist the reader in the use of the product. ARM Limited shall not be liable for any loss or damage arising from the use of any information in this document, or any error or omission in such information, or any incorrect use of the product.

Confidentiality Status

This document is Non-Confidential. The right to use, copy and disclose this document may be subject to license restrictions in accordance with the terms of the agreement entered into by ARM and the party that ARM delivered this document to.

Unrestricted Access is an ARM internal classification.

Product Status

The information in this document is final, that is for a developed product.

Conformance Notices

This section contains conformance notices.

Federal Communications Commission Notice

This device is test equipment and consequently is exempt from part 15 of the FCC Rules under section 15.103 (c).

CE Declaration of Conformity

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The system should be powered down when not in use.

The Core Tile generates, uses, and can radiate radio frequency energy and may cause harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If this equipment causes harmful interference to radio or television reception, which can be determined by turning the equipment off or on, you are encouraged to try to correct the interference by one or more of the following measures:

  • ensure attached cables do not lie across the card

  • reorient the receiving antenna

  • increase the distance between the equipment and the receiver

  • connect the equipment into an outlet on a circuit different from that to which the receiver is connected

  • consult the dealer or an experienced radio/TV technician for help.


It is recommended that wherever possible shielded interface cables be used.

Revision History
Revision A9 April 2009First release
Revision B06 July 2010Document update
Revision C20 April 2011Document update
Copyright © 2009-2011 ARM Limited. All rights reserved.ARM DUI 0441C