Other conventions

This document uses other conventions. They are described in the following sections:

Timing diagrams

The figure named Figure 1 explains the components used in timing diagrams. Variations, when they occur, have clear labels. You must not assume any timing information that is not explicit in the diagrams.

Shaded bus and signal areas are undefined, so the bus or signal can assume any value within the shaded area at that time. The actual level is unimportant and does not affect normal operation.

Figure 1. Key to timing diagram conventions

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Signals

When a signal is described as being asserted, the level depends on whether the signal is active HIGH or active LOW. Asserted means HIGH for active high signals and LOW for active low signals:

Prefix n

Active LOW signals are prefixed by a lowercase n except in the case of AXI, AHB or APB reset signals. These are named ARESETn, HRESETn and PRESETn respectively.

Prefix A

Denotes global Advanced eXtensible Interface (AXI) signals:

Prefix AR

Denotes AXI read address channel signals.

Prefix AW

Denotes AXI write address channel signals.

Prefix B

Denotes AXI write response channel signals.

Prefix C

Denotes AXI low-power interface signals.

Prefix H

AHB signals are prefixed by an upper case H.

Prefix P

APB signals are prefixed by an upper case P.

Prefix R

Denotes AXI read data channel signals.

Prefix W

Denotes AXI write data channel signals.

Bytes, Halfwords, and Words

Byte

Eight bits.

Halfword

Two bytes (16 bits).

Word

Four bytes (32 bits).

Quadword

16 contiguous bytes (128 bits).

Bits, bytes, K, and M

Suffix b

Indicates bits.

Suffix B

Indicates bytes.

Suffix K

When used to indicate an amount of memory means 1024. When used to indicate a frequency means 1000.

Suffix M

When used to indicate an amount of memory means 10242 = 1 048 576. When used to indicate a frequency means 1 000 000.

Register fields

All reserved or unused address locations must not be accessed as this can result in unpredictable behavior of the device.

All reserved or unused bits of registers must be written as zero, and ignored on read unless otherwise stated in the relevant text.

All registers bits are reset to logic 0 by a system reset unless otherwise stated in the relevant text.

Unless otherwise stated in the relevant text, all registers support read and write accesses. A write updates the contents of the register and a read returns the contents of the register.

All registers defined in this document can only be accessed using word reads and word writes, unless otherwise stated in the relevant text.

Numbering

The document numbering convention is:

<base><number>

For example:

  • 0x7B4 is a hexadecimal value of 7B4

  • 9 is a decimal value of 9

  • b00001111 is an eight-bit binary value of 00001111.

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