A.8.50. CADI::CADIBptGetList()

If the debugger attaches to a target that already has breakpoints set, this method enables the debugger to identify the breakpoints.

virtual CADIReturn_t CADI::CADIBptGetList(uint32_t startIndex, 
                                         uint32_t desiredNumOfBpts,
                                         uint32_t *actualNumOfBpts,
                                         CADIBptDescription_t *breakpoints) = 0;

where:

startIndex

is the index into the internal buffer of breakpoints held by the target.

desiredNumOfBpts

is the required number of breakpoints.

actualNumOfBpts

is the number of breakpoints that are actually returned in the buffer.

breakpoints

is an array of CADIBptDescription_t structures used to return the requested breakpoints (see CADIBptDescription_t). The array must be allocated by the caller.

Vector catching

ARM Fast Models enable vector catching, using permanent breakpoints on special purpose registers. See Table A.1 for those common to AArch32 and AArch64, and Table A.2 for those unique to AArch64. CADIBptGetList() returns these breakpoints, if present, in addition to temporary ones.

Table A.1. Special purpose registers with permanent breakpoints, by processor and technology

Cortex-A and Cortex-RTrustZoneTrustZoneVirtualization
RESET---
UNDEFINEDNS_UNDEFINED-HYP_UNDEFINED
---HYP_HYP
SVCNS_SVCSMCHVC
PREFETCH_ABORTNS_PREFETCH_ABORTMON_PREFETCH_ABORTHYP_PREFETCH_ABORT
DATA_ABORTNS_DATA_ABORTMON_DATA_ABORTHYP_DATA_ABORT
IRQNS_IRQMON_IRQHYP_IRQ
FIQNS_FIQMON_FIQHYP_FIQ

Table A.2. Special purpose registers with permanent breakpoints unique to AArch64 processors[1]

Exception levelsDescriptor
S_EL1NS_EL1EL2EL3_CURRENT_SP0_SYNC
S_EL1NS_EL1EL2EL3_CURRENT_SP0_IRQ
S_EL1NS_EL1EL2EL3_CURRENT_SP0_FIQ
S_EL1NS_EL1EL2EL3_CURRENT_SP0_ABORT
S_EL1NS_EL1EL2EL3_CURRENT_SPx_SYNC
S_EL1NS_EL1EL2EL3_CURRENT_SPx_IRQ
S_EL1NS_EL1EL2EL3_CURRENT_SPx_FIQ
S_EL1NS_EL1EL2EL3_CURRENT_SPx_ABORT
S_EL1NS_EL1EL2EL3_LOWER_64_SYNC
S_EL1NS_EL1EL2EL3_LOWER_64_IRQ
S_EL1NS_EL1EL2EL3_LOWER_64_FIQ
S_EL1NS_EL1EL2EL3_LOWER_64_ABORT
S_EL1NS_EL1EL2EL3_LOWER_32_SYNC
S_EL1NS_EL1EL2EL3_LOWER_32_IRQ
S_EL1NS_EL1EL2EL3_LOWER_32_FIQ
S_EL1NS_EL1EL2EL3_LOWER_32_ABORT

[1] The names of these registers are made up of the exception level followed by the descriptor, for example S_EL1_CURRENT_SP0_SYNC.


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