You can either view information about the caches in the Cache Data view or by using the cache list and cache print commands in
the Commands view.
Figure 6-4 Cache Data view (showing L1 TLB cache)
NoteCache awareness is dependent on the exact device and connection method.
The Cache debug mode option in the
DTSL Configuration Editor dialog enables or
disables the reading of cache RAMs in the Cache Data view.
Selecting this option enables the reading of cache RAMs every time the target stops, if
the Cache Data view is suitably configured.
Enabling the Preserve cache contents in debug state option in the
DTSL Configuration Editor preserves the cache
contents while the core is stopped. If this option is disabled, there is no guarantee
that the cache contents will be preserved when the core is stopped.
NoteFor the most accurate results, enable the Preserve cache contents in debug state option in the DTSL Configuration Editor dialog. When this option is not
enabled, the information presented might be less accurate due to debugger interactions
with the target.
Figure 6-5 DTSL Configuration Editor (Cache RAMs configuration tab)
For processors based on the ARMv8 architecture, there are restrictions on
- Cache preservation is not possible when the MMU is configured to
use the short descriptor translation table format.
- When using the long descriptor translation table format, cache
preservation is possible but the TLB contents cannot be preserved.
You can either enable the options prior to connecting to the target from the Debug Configurations dialog, or after connecting from the
Debug Control view context menu.
NoteOn some devices, reading cache data can be very slow. To avoid issues, do
not enable DTSL options that are not required. Also, if not required, close any cache
views in the user interface.
You can use the Memory view to display
the target memory from the perspective of the different caches present on the target. On
the command line, to display or read the memory from the perspective of a cache, prefix
the memory address with
the Cortex-A15 processor, possible values of
# Display memory from address 0x9000 from the perspective of the L1D cache.
# Dump memory to myFile.bin, from address 0x80009000 from the perspective of the L2 cache.
dump binary memory myFile.bin S<cacheViewID=L2>:0x80009000 0x10000
# Append to myFile.bin, memory from address 0x80009000 from the perspective of the L3 cache.
append memory myFile.bin <cacheViewID=L3>:0x80009000 0x10000