Debug units, such as DSTREAM, use JTAG to connect directly to physical devices.
To detect the devices, the debug unit sends clock signals around the JTAG scan chain,
which passes through all the physical devices in sequence. The physical devices on the
JTAG scan chain can include:
- Legacy ARM processors, such
as ARM7, ARM9, and ARM11 processors.
- ARM CoreSight Debug Access
- Unknown or custom devices that are not based on ARM.
ARM Cortex processors and CoreSight devices are not present directly on the
JTAG scan chain. Instead, ARM CoreSight Debug Access Ports provide access to CoreSight
Memory Access Ports, which in turn provide access to additional JTAG devices or
memory-mapped virtual devices, such as ARM Cortex processors and CoreSight devices. Each
virtual device provides memory-mapped registers that a debugger can use to control and
configure the device, or to read information from it.
There are different types of CoreSight devices.
- Embedded Trace Macrocell (ETM) and Program Flow Trace Macrocell (PTM) are trace
sources that attach directly to a Cortex processor and non-invasively generate
information about the operations performed by the processor. Each Cortex processor
has its own revision of ETM or PTM that has specific functionality for that
- Instrumentation Trace Macrocell (ITM) and System Trace Macrocell (STM) are trace
sources that generate trace information about software and hardware events occurring
across the System-on-Chip.
- Embedded Trace Buffer (ETB), Trace Memory Controller (TMC) and Trace Port Interface
Unit (TPIU) are trace sinks that receive trace information generated by the trace
sources. Trace sinks either store the trace information or route it to a physical
- Funnels and Replicators are trace links that route trace information from trace
sources to trace sinks.
- Cross Trigger Interface (CTI) devices route events between other devices. The CTI
network has a variety of uses, including:
- Halting processors when trace buffers become full.
- Routing trace triggers.
- Ensuring tight synchronization between processors, for example when one
processor in a cluster halts, the other processors in the cluster halt with
A debugger needs to know details of the physical JTAG scan chain, and it needs
details of individual Cortex processors and CoreSight devices, including CoreSight AP
index, ROM table base address, device type, revision, and implementation detail.
However, a debugger also needs to know how devices are connected to each other. For
example which processors are part of the same cluster, how the CTI network can pass
event information between devices, and the topology of the trace sub-system. Without
this information, a debugger might not be able to provide all of the control and
configuration services that are available.