|Non-Confidential||PDF version||ARM DUI0446Z|
|Home > Platform Configuration > About importing platform and model configurations|
The Platform Configuration Editor and Model Configuration Editor views enable you to import platform and model information into DS-5. This enables you to easily provide debug and trace support for platforms and models through RVI, DSTREAM, VSTREAM, or model connections.
The DS-5 Configuration Database holds the platform configuration and connection settings in DS-5. You can create new platform configurations in a new configuration database, which can extend the default configuration database.
To create a new configuration, DS-5 uses information from:
A configuration file, for a platform, created and saved using the Platform Configuration Editor.
A configuration file, for a model that provides a CADI server, created and saved using the Model Configuration Editor. The model can be already running or you can specify the path and filename to the executable file.
You can create the following debug operations:
Single processor and Symmetric MultiProcessing (SMP) bare-metal debug for hardware and models.
Single processor and SMP Linux kernel debug for hardware.
Linux application debug configurations for hardware.
big.LITTLE™ configurations for cores that support big.LITTLE operation, such as Cortex™-A15/Cortex-A7.
For hardware targets where a trace subsystem is present, appropriate Debug and Trace Services Layer (DTSL) options are produced. These can include:
Selection of on-chip (Embedded Trace Buffer (ETB), Micro Trace Buffer (MTB), Trace Memory Controller (TMC) or other on-chip buffer) or off-chip (DSTREAMtrace buffer) trace capture.
Cycle-accurate trace capture.
Trace capture range.
Configuration and capture of Instruction Trace Macrocell (ITM) trace to be handled by the DS-5 Event Viewer.
The Platform Configuration Editor does not create debug operations that configure non-instruction trace macrocells other than ITM.
For SMP configurations, the Cross Trigger Interface (CTI) synchronization is used on targets where a suitable CTI is present.
Using a CTI produces a much tighter synchronization with a very low latency in the order of cycles but the CTI must be fully implemented and connected in line with the ARM® reference designs, and must not be used for any other purpose. Synchronization without using a CTI has a much higher latency, but makes no assumptions about implementation or usage.
You might have to manually configure off-chip TPIU trace for multiplexed pins and also perform calibrations to cope with signal timing issues.
If you experience any problems or need to produce other configurations, contact your support representative.