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|Home > Debug and Trace Services Layer (DTSL) > Need for DTSL > SoC design complexity|
The debugger must be able to handle complex SoC designs which contain many cores and many debug components. For example, the following figure shows a relatively simple SoC design containing many debug components:
Such systems are continuing to become more complicated as time goes on. For example, SoC designers might want to use multiple sub-systems which are accessed through multiple DAPs, but which are linked by multiple Cross Trigger Interfaces (CTIs) so that they can still be synchronized. Each sub-system would have a similar design to that shown in the figure, but with shared CTIs and possibly shared TPIU.
Because system designs are so complicated, and vary so greatly, DTSL is designed to provide a layer of abstraction between the details of a particular system and the tools which provide debugging functionality to the user. For example, a debug tool using DTSL knows that there is a source of trace data for a particular core, and can access that data, but does not have to handle the complexities of system configuration and tool set-up in order to get that data. It does not have to know how to, for example, program up CoreSight™ Funnels, collect trace data from a DSTREAM, or demultiplex the TPIU trace protocol.