|Non-Confidential||PDF version||ARM DUI0446Z|
|Home > Debug and Trace Services Layer (DTSL) > DTSL support for SMP and AMP configurations > Hardware synchronization|
With hardware synchronization, the target provides synchronization features on-chip. This is typically the case for ARM® CoreSight systems that use the Cross Trigger Interface (CTI) to propagate debug halt and go requests between cores. This ability relies on the hardware design implementing this feature, and so might not be available on all CoreSight designs.