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Modern ARM® processors consist of several debug and trace components. Knowledge of what these components do and how they connect to each other is important for creating a platform configuration.
Debug units, such as DSTREAM, use JTAG to connect directly to physical devices. To detect the devices, the debug unit sends clock signals around the JTAG scan chain, which passes through all the physical devices in sequence. The physical devices on the JTAG scan chain can include:
ARM Cortex processors and CoreSight devices are not present directly on the JTAG scan chain. Instead, ARM CoreSight Debug Access Ports provide access to CoreSight Memory Access Ports, which in turn provide access to additional JTAG devices or memory-mapped virtual devices, such as ARM Cortex processors and CoreSight devices. Each virtual device provides memory-mapped registers that a debugger can use to control and configure the device, or to read information from it.
There are different types of CoreSight devices.
A debugger needs to know details of the physical JTAG scan chain, and it needs details of individual Cortex processors and CoreSight devices, including CoreSight AP index, ROM table base address, device type, revision, and implementation detail. However, a debugger also needs to know how devices are connected to each other. For example which processors are part of the same cluster, how the CTI network can pass event information between devices, and the topology of the trace sub-system. Without this information, a debugger might not be able to provide all of the control and configuration services that are available.