There is no interrupt controller on the motherboard. The IO FPGA peripheral interrupts can connect to an interrupt controller in a CoreTile Express daughterboard through the SB bus.

The IO FPGA also generates CPUIRQ, CPUFIQ, and nEvent for use by legacy cores that do not have a GIC interrupt controller.

The IO FPGA peripheral interrupts also connect to the daughterboard Site 2 and enable a processor core and interrupt controller implemented in the daughterboard FPGA to process interrupts.

You can generate the four interrupt signals INT[3:0] by the daughterboards and are input to the IO FPGA. These are returned to the daughterboards on signals IRQ[39:36] and IRQ[35:32]. The function of these is determined by the daughterboard.

Figure 2.8 shows the interrupt architecture.

For more information on interrupt handling, see the documentation for your CoreTile Express daughterboard.

Table 2.2 shows the interrupt mapping for the IRQ[47:0] signals.