Motherboard Express µATX Technical Reference ManualV2M-P1
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4.2.2. ARM Cortex-A Series memory map

Figure 4.2 shows an example of the ARM Cortex-A Series memory map when the motherboard is used with the CoreTile Express A5x2 daughterboard.

Figure 4.2. ARM Cortex-A Series system memory map as viewed from a CoreTile Express A5x2 daughterboard

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Caution

The attached daughterboard defines the address ranges for the SMB chip selects.

Table 4.2 shows the peripherals and memory on the motherboard when using the ARM Cortex-A Series memory map. The addresses are offsets are from the base addresses of the SMB chip selects.

Table 4.2. Motherboard peripheral ARM Cortex-A Series memory map

PeripheralInterface logicSMB chip selectAddress offset
NOR Flash 0-CS00x00000000-0x03FFFFFF
Reserved--0x04000000-0x07FFFFFF
NOR Flash 0-CS00x08000000-0x0BFFFFFF
NOR Flash 1-CS40x00000000-0x03FFFFFF
Reserved-CS50x00000000-0x03FFFFFF
User SRAM-CS10x00000000-0x03FFFFFF
Video SRAM CS20x00000000-0x01FFFFFF
Ethernet CS20x02000000-0x02FFFFFF
USB CS20x03000000-0x03FFFFFF
Local DAP ROM CS30x00000000-0x0000FFFF
System registersCustomCS30x00010000-0x0001FFFF
System controlARM SP810CS30x00020000-0x0002FFFF
Serial Bus PCICustomCS30x00030000-0x0003FFFF
AACIARM PL041CS30x00040000-0x0004FFFF
MMCIARM PL180CS30x00050000-0x0005FFFF
KMI0ARM PL050CS30x00060000-0x0006FFFF
KMI0ARM PL050CS30x00070000-0x0007FFFF
Reserved-CS30x00080000-0x0008FFFF
UART0ARM PL011CS30x00090000-0x0009FFFF
UART1ARM PL011CS30x000A0000-0x000AFFFF
UART2ARM PL011CS30x000B0000-0x000BFFFF
UART3ARM PL011CS30x000C0000-0x000CFFFF
Reserved-CS30x000D0000-0x000DFFFF
Reserved-CS30x000E0000-0x000EFFFF
WDTARM SP805CS30x000F0000-0x000FFFFF
Reserved-CS30x00100000-0x0010FFFF
TIMER0/1ARM SP804CS30x00110000-0x0011FFFF
TIMER2/3ARM SP804CS30x00120000-0x0012FFFF
Reserved-CS30x00130000-0x0013FFFF
Reserved-CS30x00140000-0x0014FFFF
Reserved-CS30x00150000-0x0015FFFF
Serial Bus DVICustomCS30x00160000-0x0016FFFF
RTCARM PL031CS30x00170000-0x0017FFFF
Reserved-CS30x00180000-0x0018FFFF
Reserved-CS30x00190000-0x0019FFFF
Compact FlashCustomCS30x001A0000-0x001AFFFF
UART4ARM PL011CS30x001B0000-0x001BFFFF
Reserved-CS30x001C0000-0x001CFFFF
Reserved-CS30x001D0000-0x001DFFFF
Reserved-CS30x001E0000-0x001EFFFF
CLCD controlARM PL111CS30x001F0000-0x001FFFFF
Reserved-CS30x00200000-0x03FFFFFF

Note

  • The actual address for the peripheral depends on the chip select mapping in the static memory controller in the CoreTile Express or LogicTile Express daughterboard. See the documentation for the daughterboard.

  • The daughterboards typically have additional peripherals. See the documentation for the daughterboard.

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