ARM CoreTile Express A9x4 Technical Reference ManualCortex®-A9 MPCore (V2P-CA9)
Home

ARM® CoreTile Express A9x4 Technical Reference Manual

Cortex®-A9 MPCore (V2P-CA9)

Copyright © 2009-2014, ARM. All rights reserved.

Proprietary notices

Table of Contents

Preface
About this book
Product revision status
Intended audience
Using this book
Glossary
Conventions
Additional reading
Feedback
Feedback on this product
Feedback on content
1. Introduction
1.1. About the CoreTile Express A9x4 daughterboard
1.2. Precautions
1.2.1. Ensuring safety
1.2.2. Preventing damage
2. Hardware Description
2.1. Overview of the CoreTile Express A9x4 daughterboard
2.2. Cortex-A9 MPCore test chip
2.3. System interconnect signals
2.4. Powerup configuration and resets
2.4.1. Powerup configuration
2.4.2. Resets
2.5. Clocks
2.5.1. Programmable clock generators
2.5.2. Test chip clock generators
2.5.3. External clocks
2.6. Interrupts
2.6.1. Overview of interrupts
2.6.2. Test chip interrupts
2.7. Debug
2.8. Voltage, current, and power monitoring
3. Programmers Model
3.1. About this programmers model
3.2. Daughterboard memory map
3.2.1. Remapping memory
3.2.2. Overview of the memory map for the on-chip peripherals
3.3. Programmable peripherals and interfaces
3.3.1. PrimeCell slow AXI interconnect (PL301)
3.3.2. PrimeCell fast AXI interconnect, PL301
3.3.3. Cortex-A9 MPCore multiprocessor
3.3.4. PrimeCell Color LCD Controller, PL111
3.3.5. L2 cache controller, PL310
3.3.6. Dual-Timer module, SP804
3.3.7. PrimeCell DDR2 DMC interface, PL341
3.3.8. PrimeCell SMC dual SRAM memory interface, PL354
3.3.9. Test chip SCC registers
3.3.10. TrustZone protection controller
3.3.11. Watchdog module, SP805
A. Signal Descriptions
A.1. HDRX HSB multiplexing scheme
A.2. Debug and Trace connectors
A.2.1. JTAG connector
A.2.2. Trace connector
B. Specifications
B.1. AC characteristics
C. Revisions

List of Figures

1. Key to timing diagram conventions
1.1. CoreTile Express A9x4 daughterboard layout
2.1. Daughterboard block diagram
2.2. System connect example with optional LogicTile Express 3MG daughterboard
2.3. Top-level view of the test chip components
2.4. Reset overview
2.5. Clocks overview
2.6. Test chip PLLs and clock divider logic
2.7. Interrupt overview
2.8. CoreSight and trace
3.1. Daughterboard memory map
3.2. On-chip peripheral memory map
3.3. user_config0 Register bit assignments
3.4. Test chip CFGRW0 Register bit assignments
3.5. Test chip CFGRW1 Register bit assignments
3.6. Test chip CFGRW2 Register bit assignments
A.1. HSB multiplexing

List of Tables

1.
2.1. Reset sources
2.2. Daughterboard OSCCLK clock sources
2.3. Test chip generated clocks
2.4. External clock sources
2.5. SB interrupt signals
2.6. Test chip interrupts
2.7. Test chip trace connection addresses
2.8. Device numbers for voltage monitoring
2.9. Device numbers for current monitoring
2.10. Device numbers for power monitoring
3.1. Peripheral memory map
3.2. Remap regions
3.3. DMC, PL341, register summary
3.4. DMC user_config0 Register bit assignments
3.5. DMC user_config1 Register bit assignments
3.6. DMC user_config2 Register bit assignments
3.7. DMC user_status Register bit assignments
3.8. Test chip SCC register summary
3.9. Test chip CFGRW0 Register bit assignments
3.10. Test chip CFGRW1 Register bit assignments
3.11. Test chip CFGRW2 Register bit assignments
3.12. TZPC signals
B.1. AC characteristics
C.1. Issue A
C.2. Differences between Issue A and Issue B
C.3. Differences between Issue B and Issue C
C.4. Differences between Issue C and Issue D
C.5. Differences between Issue D and Issue E
C.6. Differences between Issue E and Issue F
C.7. Differences between Issue F and Issue G
C.8. Differences between Issue G and Issue H

Proprietary Notice

Words and logos marked with ® or ™ are registered trademarks or trademarks of ARM in the EU and other countries, except as otherwise stated below in this proprietary notice. Other brands and names mentioned herein may be the trademarks of their respective owners.

Neither the whole nor any part of the information contained in, or the product described in, this document may be adapted or reproduced in any material form except with the prior written permission of the copyright holder.

The product described in this document is subject to continuous developments and improvements. All particulars of the product and its use contained in this document are given by ARM in good faith. However, all warranties implied or expressed, including but not limited to implied warranties of merchantability, or fitness for purpose, are excluded.

This document is intended only to assist the reader in the use of the product. ARM shall not be liable for any loss or damage arising from the use of any information in this document, or any error or omission in such information, or any incorrect use of the product.

Where the term ARM is used it means “ARM or any of its subsidiaries as appropriate”.

Confidentiality Status

This document is Non-Confidential. The right to use, copy and disclose this document may be subject to license restrictions in accordance with the terms of the agreement entered into by ARM and the party that ARM delivered this document to.

Product Status

The information in this document is final, that is for a developed product.

Conformance Notices

This section contains conformance notices.

Federal Communications Commission Notice

This device is test equipment and consequently is exempt from part 15 of the FCC Rules under section 15.103 (c).

CE Declaration of Conformity

To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.

The system should be powered down when not in use.

The daughterboard generates, uses, and can radiate radio frequency energy and may cause harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If this equipment causes harmful interference to radio or television reception, which can be determined by turning the equipment off or on, you are encouraged to try to correct the interference by one or more of the following measures:

  • Ensure attached cables do not lie across the card.

  • Reorient the receiving antenna.

  • Increase the distance between the equipment and the receiver.

  • Connect the equipment into an outlet on a circuit different from that to which the receiver is connected.

  • Consult the dealer or an experienced radio/TV technician for help

.

Note

It is recommended that wherever possible shielded interface cables be used.

Revision History
Revision A27 November 2009First release for V2P-CA9
Revision B26 March 2010Second release for V2P-CA9
Revision C27 August 2010Third release for V2P-CA9
Revision D15 October 2010Fourth release for V2P-CA9
Revision E28 March 2011Fifth release for V2P-CA9
Revision F12 October 2012Sixth release for V2P-CA9
Revision G31 March 2013Seventh release for V2P-CA9
Revision H29 May 2014Eighth release for V2P-CA9
Copyright © 2009-2014, ARM. All rights reserved.ARM DUI 0448H
Non-ConfidentialID052914
PDF file icon  PDF version
Home