The PISMO2 connector enables memory expansion using PISMO2
small form factor memory modules. Figure A.2 shows the PISMO2 connector, J3. See the
PISMO2 specification for pin allocation and AN224, constraint, for
FPGA connection.
Table A.1 shows
the PISMO2 voltage selection.You can use this information to set
the voltages that a PISMO module uses. Voltage regulators on the
LogicTile PCB drive the power supply output pins on the PISMO2 connector.
Some are adjustable, by jumpers J14, J23, and J25, and some are
fixed. Table A.1 shows
the variable power domains.
Note
The ARM Information Center help
section also provides a pinout for the PISMO2, SATA and HSSTP connectors
on the LogicTile. See the ARM Technical Support Knowledge Articles
section Development Boards, Versatile Express Logic Tiles.
Because of pin limitations on the FPGA, the Dynamic
Memory Address Bus DM_A is limited
to DM_A[14:0]. The maximum Dynamic
Memory size supported is 512MB.
Table A.1 shows
the PISMO2 voltage selection.
Table A.1. PISMO voltage selection
| Connector | Position | Voltage |
|---|
| DDR_VCC, J14 | 1-2 | 3V3 |
| DDR_VCC, J14 | 2-3 | 1V8 |
| DDR_VIO, J23 | 1-2 | 1V5 |
| DDR_VIO, J23 | 3-4 | 1V8 |
| DDR_VIO, J23 | 5-6 | 2V5 |
| STAT_VIO, J25 | 1-2 | 1V5 |
| STAT_VIO, J25 | 3-4 | 1V8 |
| STAT_VIO, J25 | 5-6 | 3V3 |
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