The daughterboard includes the interconnect to implement a High
Speed Serial Trace Port (HSSTP). The interconnect supports
six lanes of LVDS signaling. Figure A.7 shows the HSSTP connector, J10.
Table A.8 shows
the HSSTP pin mapping.
Caution
The LVDS Device signal pairs, TX1+ and TX1-, TX2+ and TX2-,
and TX5+ and TX5-, connect to the FPGA with their polarity reversed
from the default to improve signal integrity. Signal pairs must
be swapped in the FPGA by setting the inverted polarity input in
the instantiation of the transceiver module.
Table A.8 shows
the HSSTP pin mapping.
Table A.8. HSSTP connector, J10, signal list
| HSSTP pin | HSSTP signal | HSSTP pin | HSSTP signal |
|---|
| 1 | TX4+ | 2 | VTREF |
| 3 | TX4- | 4 | TCK |
| 5 | GND | 6 | GND |
| 7 | TX2+ | 8 | TMS |
| 9 | TX2- | 10 | nTRST |
| 11 | GND | 12 | GND |
| 13 | TX0+ | 14 | TDI |
| 15 | TX0- | 16 | TDO |
| 17 | GND | 18 | GND |
| 19 | CLK+ | 20 | nSRST |
| 21 | CLK- | 22 | DBGREQ |
| 23 | GND | 24 | GND |
| 25 | TX1+ | 26 | DBGACK |
| 27 | TX1- | 28 | RTCK |
| 29 | GND | 30 | GND |
| 31 | TX3+ | 32 | TRIGIN |
| 33 | TX3- | 34 | TRIGOUT |
| 35 | GND | 36 | GND |
| 37 | TX5+ | 38 | GND |
| 39 | TX5- | 40 | GND |
Table A.9 shows
the HSSTP TX signal FPGA-GTX connectivity.
Table A.9. HSSTP TX signal FPGA-GTX connectivity
| HSSTP signal | GTX location |
|---|
| HSSTP_TX0_P | X0Y1 |
| HSSTP_TX0_N |
| HSSTP_TX1_P | X0Y1 |
| HSSTP_TX1_N |
| HSSTP_TX2_P | X0Y0 |
| HSSTP_TX2_N |
| HSSTP_TX3_P | X0Y2 |
| HSSTP_TX3_N |
| HSSTP_TX4_P | X0Y0 |
| HSSTP_TX4_N |
| HSSTP_TX5_P | X0Y1 |
| HSSTP_TX5_N |
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