2.4. FPGA debug and trace
This section describes the debug and trace interfaces provided
on the daughterboard.
The following separate JTAG paths exist on the daughterboard:
F-JTAG, FPGA debug, using F-JTAG (ILA), J6.
P-JTAG, Processor, using J 13 to connect to a virtual
TAP controller synthesized into the FPGA.
The daughterboard supports 32-bit parallel TRACE and six lane
HSSTP. The voltage domain for TRACE and HSSTP control is 3V3. See
Application Note AN224 Example LogicTile Express 3MG
design for a Core Tile Express A9x4 for FPGA connectivity.
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