The the MCC on the motherboard controls the daughterboard
resets. Figure 2.6 shows
the resets from the motherboard and the reset acknowledge signals
from the daughterboard.
The nSRST signal from the
P-JTAG connector or an internal signal can be connected to the NAND_D[7] pin in the FPGA. This pin
connects to CB_RESTREQ using
the DCC to request an external reset. This external reset results
in CB_nRST being asserted. CB_nPOR can optionally be asserted
by the ASSERTNPOR setting, that
can be either TRUE or FALSE in the daughterboard configuration files.
See the Versatile Express Configuration Technical
Reference Manual for an example of the daughterboard
configuration file directory structure. See the Versatile
Express Configuration Technical Reference Manual for
examples of daughterboard configuration files.
Note
Only the CB_nPOR and CB_nRST signals are driven to the daughterboard
FPGA. Depending on the motherboard configuration file settings,
you can drive CB_RSTREQ from
the FPGA through the DCC to request a cold or warm reset.
Figure 2.7 shows
the basic power-up and power-down reset cycle.
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