LogicTile Express 3MG Technical Reference Manual: 2.1. Overview of the daughterboard hardware

2.1. Overview of the daughterboard hardware

Figure 2.1 shows the high-level hardware infrastructure.

The hardware infrastructure supports system expansion and a number of debug interfaces. For information on the connector pinouts to these additional interfaces, see Appendix A Signal Descriptions.

Note

A configuration image loaded into the FPGA at power-up defines the functionality of the daughterboard. The Application Note AN224 Example LogicTile Express 3MG design for a Core Tile Express A9x4, provided by ARM, implements an example AMBA system using the daughterboard. See the documentation supplied on the accompanying media and the Application Notes listinghttp://infocenter.arm.com for more information.

Figure 2.1. Hardware infrastructure

The hardware infrastructure of the daughterboard comprises:

Single Xilinx Virtex-5 XC5VLX330T FPGA:
- Up to 512KB of internal FPGA block RAM is available.
- Speed-grade -1.
256MB of NAND Flash memory for FPGA images.
16MB of on-board ZBT RAM:
- Two independent banks of 8MB are supported.
Platform Independent Storage MOdule (PISMO) connector:
- Up to 512MB of DDR memory is supported using PISMO2 small form factor memory modules.
Two High-Speed Buses (HSBs) routed to the HDRX header:
- A high speed bus Master, M, interface.
- A high speed bus Slave, S, interface.
- Low Voltage Differential Signaling (LVDS) support.
Motherboard interfaces routed to the HDRY header:
- Multi Media Bus (MMB).
- PCI-Express Bus (PCIe).
- System Bus (SB).
- Static Memory Bus (SMB).
- Configuration Bus (CB).
Serial Advanced Technology Attachment (SATA) connectors:
- A Host, H, connector.
- A Device, D, connector.
Debug interfaces:
- JTAG port for RealView^® ICE^® (RVI).
- Integrated Logic Analyzer (ILA) port for ChipScope™.
- Trace A and Trace B ports supporting up to 32-bit trace.
- High Speed Serial Trace Port (HSSTP) for prototyping of high-speed trace.
Eight general purpose Dual In-line Package (DIP) switches.
FPGA DONE LED, FPGA configured.
OverTemp LED.
Eight general purpose LEDs.
Local Daughterboard Configuration Controller (DCC) that configures the oscillators and power supplies on the daughterboard.
Battery for FPGA image AES encryption key.
On-board programmable oscillators.
Support for Serial Configuration Controller (SCC) for correct functioning of LEDs and switches.

For more information, see System interconnect.

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