The Nested Vectored
Interrupt Controller
Depending on the implementation, the Nested Vectored
Interrupt Controller (NVIC) can support:
- ARMv6-M
1,
8, 16, or 32 external interrupts with 4 different priority levels.
- ARMv7-M
up to 240 external
interrupts with up to 256 different priority levels that can be dynamically
reprioritized. The NVIC also supports the tail-chaining of interrupts.
The microcontroller profiles support both level and pulse
interrupt sources. The processor state is saved automatically in
hardware on interrupt entry and is restored on interrupt exit.
The use of an NVIC in the microcontroller profiles means that
the vector table is very different from other ARM processors consisting
of addresses not instructions. The initial stack pointer and the
address of the reset handler must be located at 0x0 and 0x4 respectively.
These addresses are loaded into the SP and PC registers by the processor
at reset.
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