ARM architecture v4T

This is an overview of the compilation tools support for ARMv4T. This variant of the ARM architecture supports 16-bit Thumb instructions and the ARM instruction set. The following table shows useful command-line options.

Table 2. Useful command-line options

Command-line optionDescription
--cpu=4TARMv4 with 16-bit Thumb.

Where name is a specific ARM processor. For example ARM7TDMI.


Where qualifier denotes one or more qualifiers for interworking and position independence. For example --apcs=/interwork.

Show/hideKey features

When compiling code for ARMv4T, the compiler supports the 16-bit Thumb instruction set. This provides greater code density, however:

  • Thumb code usually uses more instructions for a given task, making ARM code best for maximizing performance of time-critical code.

  • ARM state and associated ARM instructions are required for exception handling

  • ARM instructions are required for coprocessor accesses including cache configuration (on cached processors) and VFP.

Show/hideAlignment support

All load and store instructions must specify addresses that are aligned on a natural alignment boundary. For example:

  • LDR and STR addresses must be aligned on a word boundary

  • LDRH and STRH addresses must be aligned on a halfword boundary

  • LDRB and STRB addresses can be aligned to any boundary.

Accesses to addresses that are not on a natural alignment boundary result in unpredictable behavior. To control this you must inform the compiler, using __packed, when you want to access an unaligned address so that it can generate safe code.


Unaligned accesses, where permitted, are treated as rotated aligned accesses.

Show/hideEndian support

You can produce either little-endian or big-endian code using the compiler command-line options --littleend and --bigend respectively.

ARMv4T supports the following endian modes:


little-endian format


legacy big-endian format.

Show/hideSee also


Using the Compiler:

Compiler Reference:

Assembler Reference:

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