This is an overview of the compilation tools support for ARMv6. This variant of the ARM architecture extends the original ARM instruction set to support multi-processing and adds some extra memory model features. It supports both ARM and Thumb instruction sets. The following table shows useful command-line options.
Table 4. Useful command-line options
| Option | Description |
|---|---|
--cpu=6 | ARMv6 with 16-bit Thumb, interworking, DSP multiply, doubleword instructions, unaligned and mixed-endian support, Jazelle, and media extensions |
--cpu=6Z | ARMv6 with security extensions |
--cpu=6T2 | ARMv6 with 16-bit Thumb and 32-bit Thumb |
--cpu= | Where
|
Key featuresIn addition to the features of ARMv5TE, when compiling code for ARMv6, the compiler:
Performs instruction scheduling for the specified processor. Instructions are re-ordered to minimize interlocks and improve performance.
Generates explicit
SXTB,SXTH,UXTB,UXTHbyte or halfword extend instructions where appropriate.Generates the endian reversal instructions
REV,REV16andREVSHif it can deduce that a C expression performs an endian reversal.Generates additional Thumb instructions available in ARMv6, for example
CPS,CPY,REV,REV16,REVSH,SETEND,SXTB,SXTH,UXTB,UXTH.Uses some functions that are optimized specifically for ARMv6, for example,
memcpy().
The compiler does not generate SIMD instructions automatically from ordinary C or C++ code because these do not map well onto C expressions. You must use assembly language or intrinsics for SIMD code generation.
Some enhanced instructions are available to improve exception handling:
SRSandRFEinstructions to save and restore the Link Register (LR) and the Saved Program Status Register (SPSR)CPSsimplifies changing state, and modifying theIandFbits in the Current Program Status Register (CPSR)architectural support for vectored interrupts with a vectored interrupt controller
low-latency interrupt mode
ARM1156T2-S can enter exceptions in Thumb state using 32-bit Thumb code.
By default, the compiler uses ARMv6 unaligned access support
to speed up access to packed structures, by allowing LDR and STR instructions
to load from and store to words that are not aligned on natural
word boundaries. Structures remain unpacked unless explicitly qualified
with __packed. The following table shows the
effect of one-byte alignment when compiling for ARMv6 and earlier
architectures.
Table 5. One-byte alignment
__packed struct
{
int i;
char ch;
short sh;
} foo;
| |
Compiling for pre-ARMv6: MOV R4,R0 BL __aeabi_uread4 LDRB R1, [R4,#4] LDRSB R2,[R4,#5] LDRB R12,[R4,#6] ORR R2,R12,R2 LSL#8 | Compiling for ARMv6 and later: LDR R0, [R4,#0] LDRB R1,[R4,#4] LDRSH R2,[R4,#5] |
Code compiled for ARMv6 only runs correctly if you enable
unaligned data access support on your processor. You can control
alignment by using the U and the A bits
in the CP15 register c1, or by tying the UBITINIT input
to the processor HIGH.
Code that uses the behavior of pre-ARMv6 unaligned data accesses
can be generated by using the compiler option --no_unaligned_access.
Note
Unaligned data accesses are not available in BE-32 endian mode.
LDRD and STRD must be word aligned.
You can produce either little-endian or big-endian code using
the compiler command-line options --littleend and --bigend respectively.
ARMv6 supports the following endian modes:
- LE
little-endian format
- BE-8
big-endian format
- BE-32
legacy big-endian format.
Mixed endian systems are also possible by using SETEND and REV instructions.
By default, the compiler generates BE-8 big-endian code when
compiling for ARMv6 and big-endian. The compiler sets a flag in
the code that labels the code as BE-8. Therefore, to enable BE-8
support in the ARM processor you normally have to set the E-bit
in the CPSR.
It is possible to link legacy code with ARMv6 code for running on an ARMv6 based processor. However, in this case the linker switches the byte order of the legacy code into BE-8 mode. The resulting image is in BE-8 mode.
To use the pre-ARMv6 or legacy BE-32 mode you must tie the BIGENDINIT input
into the processor HIGH, or set the B bit
of CP15 register c1.
Note
You must link BE-32 compatible code using the linker option --be32.
Otherwise, the ARMv6 attributes causes a BE-8 image to be produced.
- Reference
Using the Assembler:
Compiler Reference:
Linker Reference:
Assembler Reference:
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