ARM architecture v7-M

This is an overview of the compilation tools support for ARMv7-M (ARMv7 architecture targeted for the microcontroller profile). Microcontroller profiles implement a programmers' model designed for fast interrupt processing, with hardware stacking of registers and support for writing interrupt handlers in high-level languages. It implements a variant of the ARMv7 protected memory system architecture and supports the 16-bit Thumb and 32-bit Thumb instruction sets only. It does not support the ARM instruction set. The following table shows useful command-line options.

Table 9. Useful command-line options

Command-line optionDescription
--cpu=7ARMv7 with 16-bit Thumb and 32-bit Thumb only and without hardware divide[a]
--cpu=7-MARMv7 microcontroller profile with 16-bit Thumb and 32-bit Thumb only and hardware divide
--cpu=name

Where name is a specific ARM processor. For example:

  • Cortex-M3 for ARMv7 with 16-bit Thumb and 32-bit Thumb only, hardware divide, ARMv6 style BE-8 and LE data endianness support, and unaligned accesses.

[a] ARM v7 is not a recognized ARM architecture. Rather, it denotes the features that are common to all of the ARMv7-A, ARMv7-R, and ARMv7-M architectures.


Show/hideKey features

Key features for ARMv7-M:

  • Supports the SDIV and UDIV instructions.

  • Supports bit-banding to enable atomic accesses to single bit values.

  • Uses interrupt intrinsics to generate CPSIE or CPSID instructions that change the current pre-emption priority (see Table 10). For example, when you use a __disable_irq intrinsic, the compiler generates a CPSID i instruction, which sets PRIMASK to 1. This raises the execution priority to 0 and prevents exceptions with a configurable priority from entering. The following table shops interrupt intrinsics.

    Table 10. Interrupt intrinsics

    IntrinsicOpcodePRIMASKFAULTMASK
    __enable_irqCPSIE i0 
    __disable_irqCPSID i1 
    __enable_fiqCPSIE f 0
    __disable_fiqCPSID f 1

Show/hideAlignment support

The data alignment behavior supported by the ARM architecture has changed significantly between ARMv4 and ARMv7. An ARMv7 implementation must support unaligned data accesses. You can control the alignment requirements of load and store instructions by using the A bit in the CP15 register c1.

Note

ARMv7 architectures do not support pre-ARMv6 alignment.

Show/hideEndian support

You can produce either little-endian or big-endian code using the compiler command-line options --littleend and --bigend respectively.

ARMv7-M supports the following endian modes:

LE

little-endian format

BE-8

big-endian format.

The ARMv7 architecture does not support the legacy BE-32 mode. If you have legacy code for ARM v7 processors that contain instructions with a big-endian byte order, then you must perform byte order reversal.

Show/hideSee also

Copyright © 2010-2012 ARM. All rights reserved.ARM DUI 0471G
Non-ConfidentialID021412