Vector table for ARMv6 and earlier, ARMv7-A and ARMv7-R profiles

The vector table for ARMv6 and earlier, ARMv7-A and ARMv7-R profiles consists of a branch or load PC instruction to the relevant handler. If required, you can include the FIQ handler at the end of the vector table to ensure it is handled as efficiently as possible, see the following example. Using a literal pool means that addresses can easily be modified later if necessary.

Example 36. Typical vector table using a literal pool

                AREA vectors, CODE, READONLY
                ENTRY
Vector_Table
                LDR pc, Reset_Addr
                LDR pc, Undefined_Addr
                LDR pc, SVC_Addr
                LDR pc, Prefetch_Addr
                LDR pc, Abort_Addr
                NOP                    ;Reserved vector
                LDR pc, IRQ_Addr
FIQ_Handler
                ; FIQ handler code - max 4kB in size

Reset_Addr      DCD Reset_Handler
Undefined_Addr  DCD Undefined_Handler
SVC_Addr        DCD SVC_Handler
Prefetch_Addr   DCD Prefetch_Handler
Abort_Addr      DCD Abort_Handler
IRQ_Addr        DCD IRQ_Handler
                ...
                END

This example assumes that you have ROM at location 0x0 on reset. Alternatively, you can use the scatter-loading mechanism to define the load and execution address of the vector table. In that case, the C library copies the vector table for you.

Note

The vector table for ARMv6 and earlier architectures supports ARM instructions only. ARMv6T2 and later architectures support both 32-bit Thumb and ARM instructions in the vector table. This does not apply to the ARMv6-M and ARMv7-M profiles.

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