The processor response to an exception

This describes the processor response to an exception. You must ensure that the exception handler saves the system state when an exception occurs and restores it on return.

Processors that support Thumb state use the same basic exception handling mechanism as processors that do not support Thumb state. An exception causes the next instruction to be fetched from the appropriate vector table entry.

When an exception is generated, the processor performs the following actions:

  1. Copies the CPSR into the appropriate SPSR. This saves the current mode, interrupt mask, and condition flags.

  2. Switches state automatically if the current state does not match the instruction set used in the exception vector table.

  3. Changes the appropriate CPSR mode bits to:

    • Change to the appropriate mode, and map in the appropriate banked out registers for that mode.

    • Disable interrupts. IRQs are disabled when any exception occurs. FIQs are disabled when an FIQ occurs and on reset.

  4. Sets the appropriate LR to the return address.

  5. Sets the PC to the vector address for the exception.

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