Determining the SVC to be called

When the SVC handler is entered, it must establish which SVC is being called. This information can be stored in bits 0-23 of the instruction itself, as shown in Figure 13, or passed in an integer register, usually one of R0-R3.

Figure 13. ARM SVC instruction

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The top-level SVC handler can load the SVC instruction relative to the LR. Do this in assembly language, C/C++ inline, or embedded assembler.

The handler must first load the SVC instruction that caused the exception into a register. At this point, the SVC LR holds the address of the instruction that follows the SVC instruction, so the SVC is loaded into the register, in this case R0, using:

    LDR R0, [lr,#-4]

The handler can then examine the comment field bits, to determine the required operation. The SVC number is extracted by clearing the top eight bits of the opcode:

    BIC R0, R0, #0xFF000000

The following example shows how you can put these instructions together to form a top-level SVC handler. For an example of a handler that deals with SVC instructions in both ARM state and Thumb state, see the Example 43 example.

Example 44. Top-level SVC handler

    AREA TopLevelSVC, CODE, READONLY   ; Name this block of code.
    EXPORT     SVC_Handler
    PUSH       {R0-R12,lr}             ; Store registers.
    LDR        R0,[lr,#-4]             ; Calculate address of SVC instruction
                                       ; and load it into R0.
    BIC        R0,R0,#0xFF000000       ; Mask off top 8 bits of instruction
                                       ; to give SVC number.
    ; Use value in R0 to determine which SVC routine to execute.
    LDM         sp!, {R0-R12,pc}^      ; Restore registers and return.

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