4.2 When to use
There are several reasons for choosing to switch between ARM and Thumb state.
When you write code for an ARM processor that supports Thumb
instructions, you probably build most of your application to run
in Thumb state. This gives the best code density. With 8-bit or
16-bit wide memory, it also gives the best performance. However,
you might want parts of your application to run in ARM state for
reasons such as:
Some parts of an application might be speed critical.
These sections might be more efficient running in ARM state than
in Thumb state.
Some systems include a small amount of fast 32-bit memory.
ARM code can be run from this without the overhead of fetching each
instruction from 8-bit or 16-bit memory.
Thumb instructions are less flexible than their
equivalent ARM instructions. Some operations are not possible in
Thumb state. A state change to ARM is required to carry out the
enable or disable interrupts, and to change mode.
accesses to coprocessors
execution of Digital Signal Processor (DSP)
math instructions that can not be performed in C language.
- Exception handling
The processor automatically enters ARM state when
a processor exception occurs. This means that the first part of
an exception handler must be coded with ARM instructions, even if
it reenters Thumb state to carry out the main processing of the
exception. At the end of such processing, the processor must be
returned to ARM state to return from the handler to the main application.
- Standalone Thumb programs
An ARM processor that supports Thumb instructions
always starts in ARM state. To run simple Thumb assembly language
programs, add an ARM header that carries out a state change to Thumb
state and then calls the main Thumb routine.
Changing to ARM state for speed or functionality reasons is
mainly a concern on processors that support Thumb without the 32-bit
encoded Thumb instructions. On processors that support the 32-bit
encoded Thumb instructions, the Thumb instruction set provides almost
the same functionality as the ARM instruction set, and similar performance
in some cases.