5.7 The processor
response to an exception
An exception handler must save the system state when an exception occurs and restore it on return.
Processors that support Thumb state use the same basic exception
handling mechanism as processors that do not support Thumb state.
An exception causes the next instruction to be fetched from the
appropriate vector table entry.
When an exception is generated, the processor performs the
Copies the CPSR
into the appropriate SPSR. This saves the current mode, interrupt
mask, and condition flags.
Switches state automatically if
the current state does not match the instruction set used in the
exception vector table.
Changes the appropriate CPSR mode bits to:
Change to the appropriate mode, and map in the appropriate
banked out registers for that mode.
Disable interrupts. IRQs are disabled when any exception
occurs. FIQs are disabled when an FIQ occurs and on reset.
Sets the appropriate LR to the return address.
Sets the PC to the vector address for the exception.