5.11 Interrupt handlers
and levels of external interrupt
The ARM processor has two levels of external interrupt, FIQ and IRQ. FIQs have higher priority than IRQs.
Both FIQ and IRQ are level-sensitive active LOW signals into the processor. For an
interrupt to be taken, the appropriate disable bit in the CPSR must be clear.
FIQs have higher priority than IRQs in the following ways:
FIQs are handled
first when multiple interrupts occur.
Handling an FIQ causes IRQs and subsequent FIQs
to be disabled, preventing them from being handled until after the
FIQ handler enables them. This is usually done by restoring the
CPSR from the SPSR at the end of the handler.
The FIQ vector is the last entry in the vector table so that
the FIQ handler can be placed directly at the vector location and
run sequentially from that address. This removes the requirement
for a branch and its associated delay, and also means that if the
system has a cache, the vector table and FIQ handler might all be
locked down in one block within it. This is important because FIQs are
designed to handle interrupts as quickly as possible. The five extra
FIQ mode banked registers enable status to be held between calls
to the handler, again increasing execution speed.
An interrupt handler must contain code to clear the source
of the interrupt.