5.33 Handling an
In microcontroller profiles, exception prioritization, nesting of exceptions, and saving of corruptible registers are handled entirely by the processor to provide efficiency and to minimize interrupt latency.
Interrupts are automatically enabled on entry to every exception handler which means that
you must remove any top-level reentrant code from projects written for other processors. If
you require interrupts to be disabled then you must handle this in your code and ensure that
they are enabled on return from an exception.
Exception handlers must clear the interrupt source.
Microcontroller profiles have no FIQ input. Any peripheral
that signals an FIQ on projects from other processors must be moved
to a high-priority external interrupt. It might be necessary to check
that the handler for this kind of interrupt does not expect to use
the banked FIQ registers, because microcontroller profiles do not
have banked registers, and you must stack R8-R12 as for any other
normal IRQ handler.
Microcontroller profiles also provide a high priority Non
Maskable Interrupt (NMI) which you cannot disable.
Simple C exception handler example
Exception handlers for microcontroller profiles are not required to save or restore the
system state and can be written as ordinary, ABI-compliant C functions. However, it is
recommended that you use the
__irq keyword to identify the function as an
interrupt routine, see the following example.
__irq void SysTickHandler(void)
printf("----- SysTick Interrupt -----");
8 byte stack alignment
The Application Binary Interface (ABI)
for the ARM Architecture requires that the stack must be 8-byte
aligned on all external interfaces, such as calls between functions
in different source files. However, code does not have to maintain
8-byte stack alignment internally, for example in leaf functions.
This means that when an IRQ occurs the stack might not be correctly
ARMv7-M processors can automatically align the stack pointer
when an exception occurs. You can enable this behavior by setting
STKALIGN (bit 9) in the Configuration Control Register at address
ARMv6-M processors always enable this behavior however, it
is recommended that you manually set STKALIGN (bit 9) so that your
image is forward compatible with ARMv7-M processors.
If you are using a revision 0 Cortex-M3 processor STKALIGN
is not supported, therefore the adjustment is not performed in hardware
and needs to be done by software. The compiler can generate code
in your IRQ handlers that correctly aligns the stack. To do this
you must prefix your IRQ handlers with
--cpu=Cortex-M3-rev0 compiler switch,