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The ARMv5TE variant of the ARM architecture provides enhanced arithmetic support for Digital Signal Processing (DSP) algorithms. It supports both ARM and Thumb instruction sets.
The following table shows useful command-line options.
Table 1-3 Useful command-line options for ARMv5TE
||ARMv5 with 16-bit Thumb instructions, interworking, DSP multiply, and double-word instructions|
||ARMv5 with 16-bit Thumb instructions, interworking, DSP multiply, double-word instructions, and Jazelle® extensionsa|
When compiling code for ARMv5TE, the compiler:
Supports improved interworking between ARM and Thumb,
Performs instruction scheduling for the specified processor. Instructions are re-ordered to minimize interlocks and improve performance.
Uses multiply and multiply-accumulate instructions that act on 16-bit data items.
Uses instruction intrinsics to generate addition and subtraction instructions that perform saturated signed arithmetic. Saturated arithmetic produces the maximum positive or negative value instead of wrapping the result if the calculation overflows the normal integer range.
Uses load (
STRD) instructions that act on
two words of data.
All load and store instructions must specify addresses that are aligned on a natural alignment boundary. For example:
must be aligned on a word boundary
must be aligned on a halfword boundary
must be aligned on a doubleword boundary
can be aligned to any boundary.
Accesses to addresses that are not on a natural alignment
boundary result in unpredictable behavior.
To control this you must inform the compiler, using
when you want to access an unaligned address so that it can generate
must specify addresses that are word-aligned, otherwise the instruction
generates an abort.
Unaligned accesses, where permitted, are treated as rotated aligned accesses.
You can produce either little-endian or big-endian code using
the compiler command-line options
ARMv5TE supports the following endian modes:
legacy big-endian format.
For more information, see the Technical Reference Manual for your processor.