1.9 ARM architecture v5TE

The ARMv5TE variant of the ARM architecture provides enhanced arithmetic support for Digital Signal Processing (DSP) algorithms. It supports both ARM and Thumb instruction sets.

The following table shows useful command-line options.

Table 1-3 Useful command-line options for ARMv5TE

Command-line option Description
--cpu=5TE ARMv5 with 16-bit Thumb instructions, interworking, DSP multiply, and double-word instructions
--cpu=5TEJ ARMv5 with 16-bit Thumb instructions, interworking, DSP multiply, double-word instructions, and Jazelle® extensionsa
--cpu=name

Where name is a specific ARM processor. For example:

  • ARM926EJ-S for ARMv5 with Thumb, Jazelle extensions, physically mapped caches and MMU.

Key features

When compiling code for ARMv5TE, the compiler:

  • Supports improved interworking between ARM and Thumb, for example BLX.

  • Performs instruction scheduling for the specified processor. Instructions are re-ordered to minimize interlocks and improve performance.

  • Uses multiply and multiply-accumulate instructions that act on 16-bit data items.

  • Uses instruction intrinsics to generate addition and subtraction instructions that perform saturated signed arithmetic. Saturated arithmetic produces the maximum positive or negative value instead of wrapping the result if the calculation overflows the normal integer range.

  • Uses load (LDRD) and store (STRD) instructions that act on two words of data.

Alignment support

All load and store instructions must specify addresses that are aligned on a natural alignment boundary. For example:

  • LDR and STR addresses must be aligned on a word boundary

  • LDRH and STRH addresses must be aligned on a halfword boundary

  • LDRD and STRD addresses must be aligned on a doubleword boundary

  • LDRB and STRB addresses can be aligned to any boundary.

Accesses to addresses that are not on a natural alignment boundary result in unpredictable behavior. To control this you must inform the compiler, using __packed, when you want to access an unaligned address so that it can generate safe code.

All LDR and STR instructions, except LDRD and STRD, must specify addresses that are word-aligned, otherwise the instruction generates an abort.

Note:

Unaligned accesses, where permitted, are treated as rotated aligned accesses.

Endian support

You can produce either little-endian or big-endian code using the compiler command-line options --littleend and --bigend respectively.

ARMv5TE supports the following endian modes:

LE

little-endian format

BE-32

legacy big-endian format.

For more information, see the Technical Reference Manual for your processor.

a

The compiler cannot generate Jazelle bytecodes.

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