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ARMv7-R is a variant of the ARMv7 architecture targeted at the real-time profile. The ARMv7-R architecture supports the ARM and Thumb instruction sets.
The following table shows useful command-line options.
Table 1-8 Useful command-line options for ARMv7-R
||ARMv7 with Thumb instructions only (no ARM instructions) but without hardware dividea|
||ARMv7 real-time profile with ARM instructions, 16-bit encoded Thumb instructions, 32-bit encoded Thumb instructions, VFP, 32-bit SIMD support, and hardware divide|
Key features for ARMv7-R:
The data alignment behavior supported by the ARM architecture
has changed significantly between ARMv4 and ARMv7. An ARMv7 implementation
provides hardware support for some unaligned data accesses using
STRH. Other data accesses must maintain alignment
You can control the alignment requirements of load and store
instructions by using the
A bit in the CP15 register
You can produce either little-endian or big-endian code using
the compiler command-line options
ARMv7-R supports the following endian modes:
ARMv7 does not support the legacy BE-32 mode. If you have legacy code for ARM v7 processors that contain instructions with a big-endian byte order, then you must perform byte order reversal.
To provide support for legacy big-endian object code, ARMv7-R supports optional
byte order reversal hardware as a static option from reset, as an ARMv7-R implementation
option. ARMv7-R includes a read-only bit in the CP15 Control Register,
SCTLR.IE, bit, that indicates the instruction endianness