|Non-Confidential||PDF version||ARM DUI0471M|
|Home > Key Features of ARM Architecture Versions > ARM architecture v7-M|
ARMv7-M is a variant of the ARMv7 architecture targeted at the microcontroller profile. It implements a variant of the ARMv7 protected memory system architecture and supports the Thumb instruction set only.
The following table shows useful command-line options.
Table 1-9 Useful command-line options for ARMv7-M
||ARMv7 with Thumb instructions only and without hardware dividea|
||ARMv7 microcontroller profile with Thumb instructions only and hardware divide|
Key features for ARMv7-M:
Cortex-M3 and Cortex-M4 processors support bit-banding to enable atomic accesses to single bit values.
Uses interrupt intrinsics to generate
instructions that change the current pre-emption priority (see the following table). For
example, when you use a
__disable_irq intrinsic, the compiler generates
CPSID i instruction, which sets
1. This raises the execution priority to
prevents exceptions with a configurable priority from entering. The following table
shows interrupt intrinsics.
Table 1-10 Interrupt intrinsics
The data alignment behavior supported by the ARM architecture has changed
significantly between ARMv4 and ARMv7-M. An ARMv7-M implementation must support unaligned
data accesses. You can control whether alignment checking is enabled or disabled by setting
or unsetting the
UNALIGN_TRP bit, bit 3, in the Configuration and Control Register (CCR).
ARMv7 architectures do not support pre-ARMv6 alignment.
You can produce either little-endian or big-endian code using
the compiler command-line options
ARMv7-M supports the following endian modes:
The ARMv7 architecture does not support the legacy BE-32 mode. If you have legacy code for ARM v7 processors that contain instructions with a big-endian byte order, then you must perform byte order reversal.