1.14 ARM architecture v7-M

ARMv7-M is a variant of the ARMv7 architecture targeted at the microcontroller profile. It implements a variant of the ARMv7 protected memory system architecture and supports the Thumb instruction set only.

The following table shows useful command-line options.

Table 1-9 Useful command-line options for ARMv7-M

Command-line option Description
--cpu=7 ARMv7 with Thumb instructions only and without hardware dividea
--cpu=7-M ARMv7 microcontroller profile with Thumb instructions only and hardware divide
--cpu=name

Where name is a specific ARM processor. For example:

  • Cortex-M3 for ARMv7 with Thumb instructions only, hardware divide, ARMv6 style BE-8 and LE data endianness support, and unaligned accesses.

Key features

Key features for ARMv7-M:

  • Supports the SDIV and UDIV instructions.

  • Cortex-M3 and Cortex-M4 processors support bit-banding to enable atomic accesses to single bit values.

  • Uses interrupt intrinsics to generate CPSIE or CPSID instructions that change the current pre-emption priority (see the following table). For example, when you use a __disable_irq intrinsic, the compiler generates a CPSID i instruction, which sets PRIMASK to 1. This raises the execution priority to 0 and prevents exceptions with a configurable priority from entering. The following table shows interrupt intrinsics.

    Table 1-10 Interrupt intrinsics

    Intrinsic Opcode PRIMASK FAULTMASK
    __enable_irq CPSIE i 0  
    __disable_irq CPSID i 1  
    __enable_fiq CPSIE f   0
    __disable_fiq CPSID f   1

Alignment support

The data alignment behavior supported by the ARM architecture has changed significantly between ARMv4 and ARMv7-M. An ARMv7-M implementation must support unaligned data accesses. You can control whether alignment checking is enabled or disabled by setting or unsetting the UNALIGN_TRP bit, bit 3, in the Configuration and Control Register (CCR).

Note:

ARMv7 architectures do not support pre-ARMv6 alignment.

Endian support

You can produce either little-endian or big-endian code using the compiler command-line options --littleend and --bigend respectively.

ARMv7-M supports the following endian modes:

LE

little-endian format

BE-8

big-endian format.

The ARMv7 architecture does not support the legacy BE-32 mode. If you have legacy code for ARM v7 processors that contain instructions with a big-endian byte order, then you must perform byte order reversal.

a

ARM v7 is not a recognized ARM architecture. Rather, it denotes the features that are common to all of the ARMv7-A, ARMv7-R, and ARMv7-M architectures.

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