3.1 Instruction intrinsics, inline and embedded assembler

Instruction intrinsics, and inline and embedded assembler are built into the compiler to enable the use of target processor features that cannot normally be accessed directly from C or C++.

Examples of such features are:

  • Saturating arithmetic.

  • Custom coprocessors.

  • The Program Status Register (PSR).

Instruction intrinsics

Instruction intrinsics provide a way of easily incorporating target processor features in C and C++ source code without resorting to complex implementations in assembly language. They have the appearance of a function call in C or C++, but are replaced during compilation by assembly language instructions.

Inline assembler

The inline assembler supports interworking with C and C++. Any register operand can be an arbitrary C or C++ expression. The inline assembler also expands complex instructions and optimizes the assembly language code.


The output object code might not correspond exactly to your input because of compiler optimization.

Embedded assembler

The embedded assembler enables you to use the full ARM assembler instruction set, including assembler directives. Embedded assembly code is assembled separately from the C and C++ code. A compiled object is produced that is then combined with the object from the compilation of the C and C++ source.

The following table summarizes the main differences between instruction intrinsics, inline assembler, and embedded assembler.

Table 3-1 Differences between instruction intrinsics, inline and embedded assembler

Feature Instruction Intrinsics Inline assembler Embedded assembler
Instruction set ARM and Thumb. ARM and Thumb. a ARM and Thumb.
ARM assembler directives None supported. None supported. All supported.
C/C++ expressions Full C/C++ expressions. Full C/C++ expressions. Constant expressions only.
Optimization of assembly code Full optimization. Full optimization. No optimization.
Inlining Automatically inlined. Automatically inlined. Can be inlined by linker if it is the right size and linker inlining is enabled.
Register access Physical registers, including PC, LR and SP.

Virtual registers except PC, LR and SP.

Physical registers, including PC, LR and SP.
Return instructions Generated automatically. Generated automatically. BX, BXJ, and BLX instructions are not supported. You must add them in your code.
BKPT instruction Supported. Not supported. Supported.

The inline assembler supports Thumb instructions in ARMv6T2, ARMv6-M, and ARMv7.

Non-ConfidentialPDF file icon PDF versionARM DUI0471M
Copyright © 2010-2016 ARM Limited or its affiliates. All rights reserved.