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|Home > Handling Processor Exceptions > Processor modes and registers in ARMv6 and earlier, ARMv7-A and ARMv7-R profiles|
The ARM architecture defines an unprivileged User mode containing 15 general purpose registers, a PC, and a CPSR. In addition, there are privileged modes, each containing a SPSR and a number of banked out registers.
Typically, an application runs in User mode, but handling exceptions requires a privileged mode. An exception changes the processor mode, and this in turn means that each exception handler has access to a certain subset of the banked out registers:
its own Stack Pointer (SP)
its own LR
its own SPSR
five additional general purpose registers (FIQ only).
Each exception handler must ensure that other registers are restored to their original contents on exit. You can do this by saving the contents of any registers that the handler requires onto its stack and restore them before returning.