5.13 Single-channel DMA transfer

An FIQ handler for a single channel uses a sequence of four instructions to handle a normal data transfer.

The following example shows an interrupt handler that performs interrupt driven I/O to memory transfers, soft DMA. The code is an FIQ handler. It uses the banked FIQ registers to maintain state between interrupts. This code is best situated at location 0x1C.

In the example code:

R8

Points to the base address of the I/O device that data is read from.

IOData

Is the offset from the base address to the 32-bit data register that is read. Reading this register clears the interrupt.

R9

Points to the memory location to which that data is being transferred.

R10

Points to the last address to transfer to.

The entire sequence for handling a normal transfer is four instructions. Insert code after the conditional return to signal that the transfer is complete.

FIQ handler

    LDR     R11, [R8, #IOData]     ; Load port data from the IO device.
    STR     R11, [R9], #4          ; Store it to memory: update the pointer.
    CMP     R9, R10                ; Reached the end ?
    SUBLSS  pc, lr, #4             ; No, so return.
                                   ; Insert transfer complete
                                   ; code here.

Byte transfers can be made by replacing the load instructions with load byte instructions. Transfers from memory to an I/O device are made by swapping the addressing modes between the load instruction and the store instruction.

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