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|Home > Handling Processor Exceptions > Vector Table Offset Register (ARMv7-M only)|
The Vector Table Offset Register locates the vector table in CODE or SRAM space.
When setting a different location, the offset must be aligned based on the number of exceptions in the table. This means that the minimal alignment is 32 words that you can use for up to 16 interrupts. For more interrupts, you must adjust the alignment by rounding up to the next power of two. For example, if you require 21 interrupts, the alignment must be on a 64-word boundary because table size is 37 words, next power of two is 64.