6.3 Interrupt-driven debug communications

Shows a simple DCC routine in which text sent from the debug tools is echoed back from the target with a change of case.

Build an executable image from this example and run it on your target using the JTAG port. See your debugger documentation for instructions on how to communicate with your target through DCC.

DCC communication between target and host debug tools

;  Copyright ARM Ltd 2008. All rights reserved.
   AREA DCC, CODE, READONLY
   ENTRY
    ; Global Variables (for assembly time substitution)
    GBLS    SCReg
      ; Debug Status and Control Register name
    GBLS    DReg
      ; Data Register name (same for reading and writing)
    GBLS    TestFull
      ; R bit mask for testing whether the data register is ready to
      ; read from.
    GBLS    TestEmpty
      ; W bit mask for testing whether the data register is ready to
      ;  write to.
    ; select which architecture group to assemble for
    IF :DEF:pre_v6             ; assemble for v6 and earlier processors
      INFO 0, "Assembling for pre_v6..."
SCReg     SETS    "c0,c0"
DReg      SETS    "c1,c0"
TestFull  SETS    "#1"
TestEmpty SETS    "#2"
    ELIF :DEF:v6_onward        ; assemble for v6 and onward processors
      INFO 0, "Assembling for v6_onward..."
SCReg     SETS    "c0,c1"
DReg      SETS    "c0,c5"
TestFull  SETS    "#0x40000000"
TestEmpty SETS    "#0x20000000"
    ELSE
      INFO 1, "No target architecture specified. See the readme for more details."
    ENDIF
    IF :DEF:pre_v6 || :DEF:v6_onward
    ; Code
pollin  
   MRC   p14,0,r3,$SCReg,0 ; Read Debug Status and Control Register
   TST   r3, $TestFull
   BEQ   pollin            ; If R bit clear then loop
read
   MRC   p14,0,r0,$DReg,0  ; read word into r0 
char_masks
   MOV   r4, #0x20         ; EOR mask to invert case of a char by
                           ; flipping bit 6.
   MOV   r5, #0xC0         ; AND mask to clear all but top 2 bits of
                           ; each char.
changeCase
   TST   r0, r5            ; Check whether character value is >0x3F
   EORNE r0, r0, r4        ; If character value >0x3F, flip bit 6
                           ; of the character to invert case
   MOV   r5, r5, LSL #0x8  ; Shift the character mask left by 1 char
   MOVS  r4, r4, LSL #0x8  ; Shift the case inverter pattern left by
                           ; 1 char.
   BNE   changeCase        ; If the inverter pattern is non-zero there
                           ; are more chars, so branch to do the next
                           ; one.
pollout
   MRC   p14,0,r3,$SCReg,0 ; Read Debug Status and Control Register
   TST   r3, $TestEmpty
   BNE   pollout           ; if W set, register still full
write
   MCR   p14,0,r0,$DReg,0  ; Write word from r0
   B     pollin            ; Loop for more words to read
    ENDIF
   END

You can convert this type of polled example to an interrupt-driven example if COMMRX and COMMTX signals from the Embedded ICE logic are connected to your interrupt controller. The read and write code can then be used in an interrupt handler.

The following examples show how to build this code:

  • To build for v6 and later output:

    armasm --predefine "v6_onward SETL {TRUE}" -g dcc.s
    armlink dcc.o -o dcc.axf --ro-base=0x8000
    
  • To build for pre-v6 output:

    armasm --predefine "pre_v6 SETL {TRUE}" -g dcc.s
    armlink dcc.o -o dcc.axf --ro-base=0x8000
    
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