5.48 Half-precision floating-point number format

The half-precision floating-point formats available are ieee and alternative. In both formats, the basic layout of the 16-bit number is the same.

The half-precision floating-point format is as follows:

Figure 5-1 Half-precision floating-point format
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   S (bit[15]):      Sign bit
   E (bits[14:10]):  Biased exponent
   T (bits[9:0]):    Mantissa.

The meanings of these fields depend on the format that is selected.

The IEEE half-precision format is as follows:

IF E==31:
   IF T==0: Value = Signed infinity
   IF T!=0: Value = Nan
             T[9] determines Quiet or Signalling:
                  0: Quiet NaN
                  1: Signalling NaN
IF 0<E<31:
   Value = (-1)^S x 2^(E-15) x (1 + (2^(-10) x T))
IF E==0:
   IF T==0: Value = Signed zero
   IF T!=0: Value = (-1)^S x 2^(-14) x (0 + (2^(-10) x T))

The alternative half-precision format is as follows:

IF 0<E<32:
   Value = (-1)^S x 2^(E-15) x (1 + (2^(-10) x T))
IF E==0:
   IF T==0: Value = Signed zero
   IF T!=0: Value = (-1)^S x 2^(-14) x (0 + (2^(-10) x T))
Related concepts
5.41 Compiler support for floating-point arithmetic
5.42 Default selection of hardware or software floating-point support
5.43 Example of hardware and software support differences for floating-point arithmetic
5.44 Vector Floating-Point (VFP) architectures
5.45 Limitations on hardware handling of floating-point arithmetic
5.46 Implementation of Vector Floating-Point (VFP) support code
5.47 Compiler and library support for half-precision floating-point numbers
5.49 Compiler support for floating-point computations and linkage
5.50 Types of floating-point linkage
5.51 Compiler options for floating-point linkage and computations
Related reference
5.52 Floating-point linkage and computational requirements of compiler options
5.53 Processors and their implicit Floating-Point Units (FPUs)
8.84 --fp16_format=format
Related information
Institute of Electrical and Electronics Engineers
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