4.5 Compiler intrinsics for controlling IRQ and FIQ interrupts

The intrinsics __disable_irq, __enable_irq, __disable_fiq and __enable_fiq control IRQ and FIQ interrupts.

You cannot use these intrinsics to change any other CPSR bits, including the mode, state, and imprecise data abort setting. This means that the intrinsics can be used only if the processor is already in a privileged mode, because the control bits of the CPSR and SPSR cannot be changed in User mode.

These intrinsics are available for all processor architectures in both ARM and Thumb state, as follows:

  • If you are compiling for processors that support ARMv6 (or later), a CPS instruction is generated inline for these functions, for example:

        CPSID  i
    
  • If you are compiling for processors that support ARMv4 or ARMv5 in ARM state, the compiler inlines a sequence of MRS and MSR instructions, for example:

        MRS  r0, CPSR
        ORR  r0, r0, #0x80
        MSR  CPSR_c, r0
    
  • If you are compiling for processors that support ARMv4 or ARMv5 in Thumb state, or if --compatible is being used, the compiler calls a helper function, for example:

        BL    __ARM_disable_irq
    
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