Condition code suffixes

The instructions that can be conditional have an optional condition code, shown in syntax descriptions as {cond}. This condition is encoded in ARM instructions, and encoded in a preceding IT instruction for Thumb instructions. An instruction with a condition code is only executed if the condition code flags in the APSR meet the specified condition.

In Thumb state on processors before ARMv6T2, the {cond} field is only permitted on certain branch instructions because there is no IT instruction on these processors.

The following table shows the condition codes that you can use and the flags they depend on.

Table 17. Condition code suffixes

SuffixFlagsMeaning
EQZ setEqual
NEZ clearNot equal
CS or HSC setHigher or same (unsigned >= )
CC or LOC clearLower (unsigned < )
MIN setNegative
PLN clearPositive or zero
VSV setOverflow
VCV clearNo overflow
HIC set and Z clearHigher (unsigned >)
LSC clear or Z setLower or same (unsigned <=)
GEN and V the sameSigned >=
LTN and V differSigned <
GTZ clear, N and V the sameSigned >
LEZ set, N and V differSigned <=
ALAnyAlways. This suffix is normally omitted.

The following is an example of conditional execution.

Example 20. 

    ADD     r0, r1, r2    ; r0 = r1 + r2, don't update flags
    ADDS    r0, r1, r2    ; r0 = r1 + r2, and update flags
    ADDSCS  r0, r1, r2    ; If C flag set then r0 = r1 + r2, and update flags
    CMP     r0, r1        ; update flags based on r0-r1.

Show/hideSee also

Copyright © 2010-2011 ARM. All rights reserved.ARM DUI 0473C
Non-ConfidentialID080411