The instructions that can be conditional have an optional
condition code, shown in syntax descriptions as {.
This condition is encoded in ARM instructions, and encoded in a preceding cond}IT instruction
for Thumb instructions. An instruction with a condition code is
only executed if the condition code flags in the APSR meet the specified
condition.
In Thumb state on processors before ARMv6T2, the { field
is only permitted on certain branch instructions because there is
no cond}IT instruction on these processors.
The following table shows the condition codes that you can use and the flags they depend on.
Table 17. Condition code suffixes
| Suffix | Flags | Meaning |
|---|---|---|
EQ | Z set | Equal |
NE | Z clear | Not equal |
CS or HS | C set | Higher or same (unsigned >= ) |
CC or LO | C clear | Lower (unsigned < ) |
MI | N set | Negative |
PL | N clear | Positive or zero |
VS | V set | Overflow |
VC | V clear | No overflow |
HI | C set and Z clear | Higher (unsigned >) |
LS | C clear or Z set | Lower or same (unsigned <=) |
GE | N and V the
same | Signed >= |
LT | N and V differ | Signed < |
GT | Z clear, N and V the
same | Signed > |
LE | Z set, N and V differ | Signed <= |
AL | Any | Always. This suffix is normally omitted. |
The following is an example of conditional execution.
Example 20.
ADD r0, r1, r2 ; r0 = r1 + r2, don't update flags
ADDS r0, r1, r2 ; r0 = r1 + r2, and update flags
ADDSCS r0, r1, r2 ; If C flag set then r0 = r1 + r2, and update flags
CMP r0, r1 ; update flags based on r0-r1.
See also
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