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Home > NEON and VFP Programming > Extension register bank mapping |

NEON and VFP use the same extension register bank. This is distinct from the ARM register bank. The extension register bank is a collection of registers which can be accessed as either 32-bit, 64-bit, or 128-bit registers, depending on whether the instruction is NEON or VFP.

Figure 2 shows
the three views of the extension register bank, and the overlap between
the different size registers. For example, the 128-bit register `Q0`

is
an alias for two consecutive 64-bit registers `D0`

and `D1`

,
and is also an alias for four consecutive 32-bit registers `S0`

, `S1`

, `S2`

,
and `S3`

. The 128-bit register `Q8`

is
an alias for 2 consecutive 64-bit registers `D16`

and `D17`

but
does not have an alias using the 32-bit "`S`

"
registers.`n`

If your processor has both NEON and VFP, all the NEON registers overlap with the VFP registers.

The aliased views enables half-precision, single-precision, and double-precision values, and NEON vectors to coexist in different non-overlapped registers at the same time.

You can also use the same overlapped registers to store half-precision, single-precision, and double-precision values, and NEON vectors at different times.

Do not attempt to use overlapped 32-bit and 64-bit, or 128-bit registers at the same time because it creates meaningless results.

The mapping between the registers is as follows:

`S<2n>`

maps to the least significant half of`D<n>`

`S<2n+1>`

maps to the most significant half of`D<n>`

`D<2n>`

maps to the least significant half of`Q<n>`

`D<2n+1>`

maps to the most significant half of`Q<n>`

.

For example, you can access the least significant half of
the elements of a vector in `Q6`

by referring to `D12`

,
and the most significant half of the elements by referring to `D13`

.