This describes the assembly programming of NEON and the VFP coprocessor:
Architecture support for NEON and VFP
Half-precision extension
Fused Multiply-Add extension
Extension register bank mapping
NEON views of the register bank
VFP views of the extension register bank
Load values to VFP and NEON registers
Conditional execution of NEON and VFP instructions
Floating-point exceptions
NEON and VFP data types
NEON vectors
Normal NEON instructions
Long NEON instructions
Wide NEON instructions
Narrow NEON instructions
Saturating NEON instructions
NEON scalars
Extended notation
Polynomial arithmetic over {0,1}
NEON and VFP system registers
FPSCR, the floating-point status and control register
FPEXC, the floating-point exception register
FPSID, the floating-point system ID register
Flush-to-zero mode
When to use flush-to-zero mode
The effects of using flush-to-zero mode
Operations not affected by flush-to-zero mode
VFP vector mode
Vectors in the VFP extension register bank
VFP vector wrap-around
VFP vector stride
Restriction on vector length
Control of scalar, vector, and mixed operations
VFP directives and vector notation
Pre-UAL VFP mnemonics
Vector notation
VFPASSERT SCALAR
VFPASSERT VECTOR.