ARM® Compiler armasm User Guide

Version 5.05


Table of Contents

Preface
About this book
Using this book
Glossary
Typographic conventions
Feedback
Other information
1 Overview of the Assembler
1.1 About the ARM Compiler toolchain assemblers
1.2 Key features of the assembler
1.3 How the assembler works
1.4 Directives that can be omitted in pass 2 of the assembler
2 Overview of the ARM Architecture
2.1 About the ARM architecture
2.2 ARM, Thumb, and ThumbEE instruction sets
2.3 Changing between ARM, Thumb, and ThumbEE state
2.4 Processor modes, and privileged and unprivileged software execution
2.5 Processor modes in ARMv6-M and ARMv7-M
2.6 NEON technology
2.7 VFP hardware
2.8 ARM registers
2.9 General-purpose registers
2.10 Register accesses
2.11 Predeclared core register names
2.12 Predeclared extension register names
2.13 Predeclared XScale register names
2.14 Predeclared coprocessor names
2.15 Program Counter
2.16 Application Program Status Register
2.17 The Q flag
2.18 Current Program Status Register
2.19 Saved Program Status Registers
2.20 ARM and Thumb instruction set overview
2.21 Access to the inline barrel shifter
3 Structure of Assembly Language Modules
3.1 Syntax of source lines in assembly language
3.2 Literals
3.3 ELF sections and the AREA directive
3.4 An example ARM assembly language module
4 Writing ARM Assembly Language
4.1 About the Unified Assembler Language
4.2 Register usage in subroutine calls
4.3 Load immediate values
4.4 Load immediate values using MOV and MVN
4.5 Load immediate values using MOV32
4.6 Load immediate values using LDR Rd, =const
4.7 Literal pools
4.8 Load addresses into registers
4.9 Load addresses to a register using ADR
4.10 Load addresses to a register using ADRL
4.11 Load addresses to a register using LDR Rd, =label
4.12 Other ways to load and store registers
4.13 Load and store multiple register instructions
4.14 Load and store multiple register instructions in ARM and Thumb
4.15 Stack implementation using LDM and STM
4.16 Stack operations for nested subroutines
4.17 Block copy with LDM and STM
4.18 Memory accesses
4.19 The Read-Modify-Write operation
4.20 Optional hash with immediate constants
4.21 About macros
4.22 Test-and-branch macro example
4.23 Unsigned integer division macro example
4.24 Instruction and directive relocations
4.25 Symbol versions
4.26 Frame directives
4.27 Exception tables and Unwind tables
4.28 Assembly language changes after RVCT v2.1
5 Condition Codes
5.1 Conditional instructions
5.2 Conditional execution in ARM state
5.3 Conditional execution in Thumb state
5.4 Updates to the condition flags
5.5 Condition code suffixes
5.6 Comparison of condition code meanings in integer and floating-point code
5.7 Benefits of using conditional execution
5.8 Illustration of the benefits of using conditional instructions
5.9 Optimization for execution speed
6 Using the Assembler
6.1 Assembler command-line syntax
6.2 Specify command-line options with an environment variable
6.3 Overview of via files
6.4 Via file syntax rules
6.5 Using stdin to input source code to the assembler
6.6 Built-in variables and constants
6.7 Identifying versions of armasm in source code
6.8 Diagnostic messages
6.9 Interlocks diagnostics
6.10 Automatic IT block generation
6.11 Thumb branch target alignment
6.12 Thumb code size diagnostics
6.13 ARM and Thumb instruction portability diagnostics
6.14 Instruction width diagnostics
6.15 Two pass assembler diagnostics
6.16 Conditional assembly
6.17 Using the C preprocessor
6.18 Address alignment
6.19 Instruction width selection in Thumb
7 Symbols, Literals, Expressions, and Operators
7.1 Symbol naming rules
7.2 Variables
7.3 Numeric constants
7.4 Assembly time substitution of variables
7.5 Register-relative and PC-relative expressions
7.6 Labels
7.7 Labels for PC-relative addresses
7.8 Labels for register-relative addresses
7.9 Labels for absolute addresses
7.10 Numeric local labels
7.11 Syntax of numeric local labels
7.12 String expressions
7.13 String literals
7.14 Numeric expressions
7.15 Syntax of numeric literals
7.16 Syntax of floating-point literals
7.17 Logical expressions
7.18 Logical literals
7.19 Unary operators
7.20 Binary operators
7.21 Multiplicative operators
7.22 String manipulation operators
7.23 Shift operators
7.24 Addition, subtraction, and logical operators
7.25 Relational operators
7.26 Boolean operators
7.27 Operator precedence
7.28 Difference between operator precedence in assembly language and C
8 NEON and VFP Programming
8.1 Architecture support for NEON and VFP
8.2 Half-precision extension
8.3 Fused Multiply-Add extension
8.4 Extension register bank mapping
8.5 NEON views of the register bank
8.6 VFP views of the extension register bank
8.7 Load values to VFP and NEON registers
8.8 Conditional execution of NEON and VFP instructions
8.9 Floating-point exceptions
8.10 NEON and VFP data types
8.11 NEON vectors
8.12 Normal, long, wide, and narrow NEON operation
8.13 Saturating NEON instructions
8.14 NEON scalars
8.15 Extended notation
8.16 Polynomial arithmetic over {0,1}
8.17 NEON and VFP system registers
8.18 Flush-to-zero mode
8.19 When to use flush-to-zero mode
8.20 The effects of using flush-to-zero mode
8.21 Operations not affected by flush-to-zero mode
8.22 VFP vector mode
8.23 Vectors in the VFP extension register bank
8.24 VFP vector wrap-around
8.25 VFP vector stride
8.26 Restriction on vector length
8.27 Control of scalar, vector, and mixed operations
8.28 Overview of VFP directives and vector notation
8.29 Pre-UAL VFP syntax and mnemonics
8.30 Vector notation
8.31 VFPASSERT SCALAR
8.32 VFPASSERT VECTOR
9 Assembler Command-line Options
9.1 --16
9.2 --32
9.3 --apcs=qualifier…qualifier
9.4 --arm
9.5 --arm_only
9.6 --bi
9.7 --bigend
9.8 --brief_diagnostics, --no_brief_diagnostics
9.9 --checkreglist
9.10 --compatible=name
9.11 --cpreproc
9.12 --cpreproc_opts=options
9.13 --cpu=list
9.14 --cpu=name
9.15 --debug
9.16 --depend=dependfile
9.17 --depend_format=string
9.18 --device=name
9.19 --diag_error=tag[,tag,…]
9.20 --diag_remark=tag[,tag,…]
9.21 --diag_style={arm|ide|gnu}
9.22 --diag_suppress=tag[,tag,…]
9.23 --diag_warning=tag[,tag,…]
9.24 --dllexport_all
9.25 --dwarf2
9.26 --dwarf3
9.27 --errors=errorfile
9.28 --execstack, --no_execstack
9.29 --execute_only
9.30 --exceptions, --no_exceptions
9.31 --exceptions_unwind, --no_exceptions_unwind
9.32 --fpmode=model
9.33 --fpu=list
9.34 --fpu=name
9.35 -g
9.36 --help
9.37 -idir{,dir, …}
9.38 --keep
9.39 --length=n
9.40 --li
9.41 --library_type=lib
9.42 --licretry
9.43 --list=file
9.44 --list=
9.45 --littleend
9.46 -m
9.47 --maxcache=n
9.48 --md
9.49 --no_code_gen
9.50 --no_esc
9.51 --no_hide_all
9.52 --no_regs
9.53 --no_terse
9.54 --no_warn
9.55 -o filename
9.56 --pd
9.57 --predefine "directive"
9.58 --reduce_paths, --no_reduce_paths
9.59 --regnames=none
9.60 --regnames=callstd
9.61 --regnames=all
9.62 --report-if-not-wysiwyg
9.63 --show_cmdline
9.64 --split_ldm
9.65 --thumb
9.66 --thumbx
9.67 --unaligned_access, --no_unaligned_access
9.68 --unsafe
9.69 --untyped_local_labels
9.70 --version_number
9.71 --via=filename
9.72 --vsn
9.73 --width=n
9.74 --xref
10 ARM and Thumb Instructions
10.1 ARM and Thumb instruction summary
10.2 Instruction width specifiers
10.3 Flexible second operand (Operand2)
10.4 Syntax of Operand2 as a constant
10.5 Syntax of Operand2 as a register with optional shift
10.6 Shift operations
10.7 Saturating instructions
10.8 Condition codes
10.9 ADC
10.10 ADD
10.11 ADR (PC-relative)
10.12 ADR (register-relative)
10.13 ADRL pseudo-instruction
10.14 AND
10.15 ASR
10.16 B
10.17 BFC
10.18 BFI
10.19 BIC
10.20 BKPT
10.21 BL
10.22 BLX
10.23 BX
10.24 BXJ
10.25 CBZ and CBNZ
10.26 CDP and CDP2
10.27 CLREX
10.28 CLZ
10.29 CMP and CMN
10.30 CPS
10.31 CPY pseudo-instruction
10.32 DBG
10.33 DMB
10.34 DSB
10.35 EOR
10.36 ERET
10.37 HVC
10.38 ISB
10.39 IT
10.40 LDC and LDC2
10.41 LDM
10.42 LDR (immediate offset)
10.43 LDR (PC-relative)
10.44 LDR (register offset)
10.45 LDR (register-relative)
10.46 LDR pseudo-instruction
10.47 LDR, unprivileged
10.48 LDREX
10.49 LSL
10.50 LSR
10.51 MAR
10.52 MCR and MCR2
10.53 MCRR and MCRR2
10.54 MIA, MIAPH, and MIAxy
10.55 MLA
10.56 MLS
10.57 MOV
10.58 MOV32 pseudo-instruction
10.59 MOVT
10.60 MRA
10.61 MRC and MRC2
10.62 MRRC and MRRC2
10.63 MRS (PSR to general-purpose register)
10.64 MRS (system coprocessor register to ARM register)
10.65 MSR (ARM register to system coprocessor register)
10.66 MSR (general-purpose register to PSR)
10.67 MUL
10.68 MVN
10.69 NEG pseudo-instruction
10.70 NOP
10.71 ORN (Thumb only)
10.72 ORR
10.73 PKHBT and PKHTB
10.74 PLD, PLDW, and PLI
10.75 POP
10.76 PUSH
10.77 QADD
10.78 QADD8
10.79 QADD16
10.80 QASX
10.81 QDADD
10.82 QDSUB
10.83 QSAX
10.84 QSUB
10.85 QSUB8
10.86 QSUB16
10.87 RBIT
10.88 REV
10.89 REV16
10.90 REVSH
10.91 RFE
10.92 ROR
10.93 RRX
10.94 RSB
10.95 RSC
10.96 SADD8
10.97 SADD16
10.98 SASX
10.99 SBC
10.100 SBFX
10.101 SDIV
10.102 SEL
10.103 SETEND
10.104 SEV
10.105 SHADD8
10.106 SHADD16
10.107 SHASX
10.108 SHSAX
10.109 SHSUB8
10.110 SHSUB16
10.111 SMC
10.112 SMLAxy
10.113 SMLAD
10.114 SMLAL
10.115 SMLALD
10.116 SMLALxy
10.117 SMLAWy
10.118 SMLSD
10.119 SMLSLD
10.120 SMMLA
10.121 SMMLS
10.122 SMMUL
10.123 SMUAD
10.124 SMULxy
10.125 SMULL
10.126 SMULWy
10.127 SMUSD
10.128 SRS
10.129 SSAT
10.130 SSAT16
10.131 SSAX
10.132 SSUB8
10.133 SSUB16
10.134 STC and STC2
10.135 STM
10.136 STR (immediate offset)
10.137 STR (register offset)
10.138 STR, unprivileged
10.139 STREX
10.140 SUB
10.141 SUBS pc, lr
10.142 SVC
10.143 SWP and SWPB
10.144 SXTAB
10.145 SXTAB16
10.146 SXTAH
10.147 SXTB
10.148 SXTB16
10.149 SXTH
10.150 SYS
10.151 TBB and TBH
10.152 TEQ
10.153 TST
10.154 UADD8
10.155 UADD16
10.156 UASX
10.157 UBFX
10.158 UDIV
10.159 UHADD8
10.160 UHADD16
10.161 UHASX
10.162 UHSAX
10.163 UHSUB8
10.164 UHSUB16
10.165 UMAAL
10.166 UMLAL
10.167 UMULL
10.168 UND pseudo-instruction
10.169 UQADD8
10.170 UQADD16
10.171 UQASX
10.172 UQSAX
10.173 UQSUB8
10.174 UQSUB16
10.175 USAD8
10.176 USADA8
10.177 USAT
10.178 USAT16
10.179 USAX
10.180 USUB8
10.181 USUB16
10.182 UXTAB
10.183 UXTAB16
10.184 UXTAH
10.185 UXTB
10.186 UXTB16
10.187 UXTH
10.188 WFE
10.189 WFI
10.190 YIELD
11 NEON and VFP Instructions
11.1 Summary of NEON instructions
11.2 Summary of shared NEON and VFP instructions
11.3 Summary of VFP instructions
11.4 Interleaving provided by load and store element and structure instructions
11.5 Alignment restrictions in load and store element and structure instructions
11.6 VABA and VABAL
11.7 VABD and VABDL
11.8 VABS
11.9 VABS (floating-point)
11.10 VACLE, VACLT, VACGE and VACGT
11.11 VADD (floating-point)
11.12 VADD
11.13 VADDHN
11.14 VADDL and VADDW
11.15 VAND (immediate)
11.16 VAND (register)
11.17 VBIC (immediate)
11.18 VBIC (register)
11.19 VBIF
11.20 VBIT
11.21 VBSL
11.22 VCEQ (immediate #0)
11.23 VCEQ (register)
11.24 VCGE (immediate #0)
11.25 VCGE (register)
11.26 VCGT (immediate #0)
11.27 VCGT (register)
11.28 VCLE (immediate #0)
11.29 VCLE (register)
11.30 VCLS
11.31 VCLT (immediate #0)
11.32 VCLT (register)
11.33 VCLZ
11.34 VCMP, VCMPE
11.35 VCNT
11.36 VCVT (between fixed-point or integer, and floating-point)
11.37 VCVT (between half-precision and single-precision floating-point)
11.38 VCVT (between single-precision and double-precision)
11.39 VCVT (between floating-point and integer)
11.40 VCVT (between floating-point and fixed-point)
11.41 VCVTB, VCVTT (half-precision extension)
11.42 VDIV
11.43 VDUP
11.44 VEOR
11.45 VEXT
11.46 VFMA, VFMS
11.47 VFMA, VFMS, VFNMA, VFNMS
11.48 VHADD
11.49 VHSUB
11.50 VLDn (single n-element structure to one lane)
11.51 VLDn (single n-element structure to all lanes)
11.52 VLDn (multiple n-element structures)
11.53 VLDM
11.54 VLDR
11.55 VLDR (post-increment and pre-decrement)
11.56 VLDR pseudo-instruction
11.57 VMAX and VMIN
11.58 VMLA
11.59 VMLA (by scalar)
11.60 VMLA (floating-point)
11.61 VMLAL (by scalar)
11.62 VMLAL
11.63 VMLS (by scalar)
11.64 VMLS
11.65 VMLS (floating-point)
11.66 VMLSL
11.67 VMLSL (by scalar)
11.68 VMOV (floating-point)
11.69 VMOV (immediate)
11.70 VMOV (register)
11.71 VMOV (between one ARM register and single precision VFP)
11.72 VMOV (between two ARM registers and an extension register)
11.73 VMOV (between an ARM register and a NEON scalar)
11.74 VMOVL
11.75 VMOVN
11.76 VMOV2
11.77 VMRS
11.78 VMSR
11.79 VMUL
11.80 VMUL (floating-point)
11.81 VMUL (by scalar)
11.82 VMULL
11.83 VMULL (by scalar)
11.84 VMVN (register)
11.85 VMVN (immediate)
11.86 VNEG (floating-point)
11.87 VNEG
11.88 VNMLA (floating-point)
11.89 VNMLS (floating-point)
11.90 VNMUL (floating-point)
11.91 VORN (register)
11.92 VORN (immediate)
11.93 VORR (register)
11.94 VORR (immediate)
11.95 VPADAL
11.96 VPADD
11.97 VPADDL
11.98 VPMAX and VPMIN
11.99 VPOP
11.100 VPUSH
11.101 VQABS
11.102 VQADD
11.103 VQDMLAL and VQDMLSL (by vector or by scalar)
11.104 VQDMULH (by vector or by scalar)
11.105 VQDMULL (by vector or by scalar)
11.106 VQMOVN and VQMOVUN
11.107 VQNEG
11.108 VQRDMULH (by vector or by scalar)
11.109 VQRSHL (by signed variable)
11.110 VQRSHRN and VQRSHRUN (by immediate)
11.111 VQSHL (by signed variable)
11.112 VQSHL and VQSHLU (by immediate)
11.113 VQSHRN and VQSHRUN (by immediate)
11.114 VQSUB
11.115 VRADDHN
11.116 VRECPE
11.117 VRECPS
11.118 VREV16, VREV32, and VREV64
11.119 VRHADD
11.120 VRSHL (by signed variable)
11.121 VRSHR (by immediate)
11.122 VRSHRN (by immediate)
11.123 VRSQRTE
11.124 VRSQRTS
11.125 VRSRA (by immediate)
11.126 VRSUBHN
11.127 VSHL (by immediate)
11.128 VSHL (by signed variable)
11.129 VSHLL (by immediate)
11.130 VSHR (by immediate)
11.131 VSHRN (by immediate)
11.132 VSLI
11.133 VSQRT
11.134 VSRA (by immediate)
11.135 VSRI
11.136 VSTM
11.137 VSTn (multiple n-element structures)
11.138 VSTn (single n-element structure to one lane)
11.139 VSTR
11.140 VSTR (post-increment and pre-decrement)
11.141 VSUB (floating-point)
11.142 VSUB
11.143 VSUBHN
11.144 VSUBL and VSUBW
11.145 VSWP
11.146 VTBL and VTBX
11.147 VTRN
11.148 VTST
11.149 VUZP
11.150 VZIP
12 Wireless MMX Technology Instructions
12.1 About Wireless MMX Technology instructions
12.2 WRN and WCN directives to support Wireless MMX Technology
12.3 Frame directives and Wireless MMX Technology
12.4 Wireless MMX load and store instructions
12.5 Wireless MMX Technology and XScale instructions
12.6 Wireless MMX instructions
12.7 Wireless MMX pseudo-instructions
13 Directives Reference
13.1 Alphabetical list of directives
13.2 About assembly control directives
13.3 About frame directives
13.4 ALIAS
13.5 ALIGN
13.6 AREA
13.7 ARM or CODE32
13.8 ASSERT
13.9 ATTR
13.10 CN
13.11 CODE16
13.12 COMMON
13.13 CP
13.14 DATA
13.15 DCB
13.16 DCD and DCDU
13.17 DCDO
13.18 DCFD and DCFDU
13.19 DCFS and DCFSU
13.20 DCI
13.21 DCQ and DCQU
13.22 DCW and DCWU
13.23 END
13.24 ENDFUNC or ENDP
13.25 ENTRY
13.26 EQU
13.27 EXPORT or GLOBAL
13.28 EXPORTAS
13.29 FIELD
13.30 FRAME ADDRESS
13.31 FRAME POP
13.32 FRAME PUSH
13.33 FRAME REGISTER
13.34 FRAME RESTORE
13.35 FRAME RETURN ADDRESS
13.36 FRAME SAVE
13.37 FRAME STATE REMEMBER
13.38 FRAME STATE RESTORE
13.39 FRAME UNWIND ON
13.40 FRAME UNWIND OFF
13.41 FUNCTION or PROC
13.42 GBLA, GBLL, and GBLS
13.43 GET or INCLUDE
13.44 IF, ELSE, ENDIF, and ELIF
13.45 IMPORT and EXTERN
13.46 INCBIN
13.47 INFO
13.48 KEEP
13.49 LCLA, LCLL, and LCLS
13.50 LTORG
13.51 MACRO and MEND
13.52 MAP
13.53 MEXIT
13.54 NOFP
13.55 OPT
13.56 QN, DN, and SN
13.57 RELOC
13.58 REQUIRE
13.59 REQUIRE8 and PRESERVE8
13.60 RLIST
13.61 RN
13.62 ROUT
13.63 SETA, SETL, and SETS
13.64 SPACE or FILL
13.65 THUMB
13.66 THUMBX
13.67 TTL and SUBT
13.68 WHILE and WEND
A Assembler Document Revisions
A.1 Revisions for armasm User Guide

List of Figures

2-1 Organization of general-purpose registers and Program Status Registers
8-1 Extension register bank
8-2 VFPv2 register banks
8-3 VFPv3 register banks
10-1 ASR #3
10-2 LSR #3
10-3 LSL #3
10-4 ROR #3
10-5 RRX
11-1 De-interleaving an array of 3-element structures
11-2 Operation of doubleword VEXT for imm = 3
11-3 Example of operation of VPADAL (in this case for data type I16)
11-4 Example of operation of VPADD (in this case, for data type I16)
11-5 Example of operation of doubleword VPADDL (in this case, for data type S16)
11-6 Operation of quadword VSHL.64 Qd, Qm, #1
11-7 Operation of quadword VSLI.64 Qd, Qm, #1
11-8 Operation of doubleword VSRI.64 Dd, Dm, #2
11-9 Operation of doubleword VTRN.8
11-10 Operation of doubleword VTRN.32

List of Tables

2-1 ARM processor modes
2-2 Predeclared core registers
2-3 Predeclared extension registers
2-4 Predeclared XScale registers
2-5 Predeclared Wireless MMX registers
2-6 Predeclared coprocessor registers
2-7 Instruction groups
4-1 ARM state immediate values (8-bit)
4-2 ARM state immediate values in MOV instructions
4-3 32-bit Thumb immediate values
4-4 32-bit Thumb immediate values in MOV instructions
4-5 Stack-oriented suffixes and equivalent addressing mode suffixes
4-6 Suffixes for load and store multiple instructions
4-7 Changes from earlier ARM assembly language
4-8 Relaxation of requirements
4-9 Differences between pre-UAL Thumb syntax and UAL syntax
5-1 Condition code suffixes
5-2 Condition codes
5-3 Conditional branches only
5-4 All instructions conditional
6-1 Built-in variables
6-2 Built-in Boolean constants
6-3 Predefined macros
6-4 {TARGET_ARCH_ARM} in relation to {TARGET_ARCH_THUMB}
6-5 Command-line options
6-6 armcc equivalent command-line options
7-1 Unary operators that return strings
7-2 Unary operators that return numeric or logical values
7-3 Multiplicative operators
7-4 String manipulation operators
7-5 Shift operators
7-6 Addition, subtraction, and logical operators
7-7 Relational operators
7-8 Boolean operators
7-9 Operator precedence in ARM assembly language
7-10 Operator precedence in C
8-1 NEON data type specifiers
8-2 VFP data type specifiers
8-3 NEON saturation ranges
8-4 Pre-UAL VFP mnemonics
8-5 Floating-point values for use with FCONST
9-1 Compatible processor or architecture combinations
9-2 Supported ARM architectures
9-3 Severity of diagnostic messages
9-4 Specifying a command-line option and an AREA directive for GNU-stack sections
10-1 Summary of ARM and Thumb instructions
10-2 Condition code suffixes
10-3 PC-relative offsets
10-4 Register-relative offsets
10-5 B instruction availability and range
10-6 BL instruction availability and range
10-7 BLX instruction availability and range
10-8 BX instruction availability and range
10-9 BXJ instruction availability and range
10-10 Offsets and architectures, LDR, word, halfword, and byte
10-11 PC-relative offsets
10-12 Options and architectures, LDR (register offsets)
10-13 Register-relative offsets
10-14 Offsets and architectures, LDR (User mode)
10-15 Offsets and architectures, STR, word, halfword, and byte
10-16 Options and architectures, STR (register offsets)
10-17 Offsets and architectures, STR (User mode)
10-18 Range and encoding of expr
11-1 Summary of NEON instructions
11-2 Summary of shared NEON and VFP instructions
11-3 Summary of VFP instructions
11-4 Patterns for immediate value in VBIC (immediate)
11-5 Permitted combinations of parameters for VLDn (single n-element structure to one lane)
11-6 Permitted combinations of parameters for VLDn (single n-element structure to all lanes)
11-7 Permitted combinations of parameters for VLDn (multiple n-element structures)
11-8 Available immediate values in VMOV (immediate)
11-9 Available immediate values in VMVN (immediate)
11-10 Patterns for immediate value in VORR (immediate)
11-11 Available immediate ranges in VQRSHRN and VQRSHRUN (by immediate)
11-12 Available immediate ranges in VQSHL and VQSHLU (by immediate)
11-13 Available immediate ranges in VQSHRN and VQSHRUN (by immediate)
11-14 Results for out-of-range inputs in VRECPE
11-15 Results for out-of-range inputs in VRECPS
11-16 Available immediate ranges in VRSHR (by immediate)
11-17 Available immediate ranges in VRSHRN (by immediate)
11-18 Results for out-of-range inputs in VRSQRTE
11-19 Results for out-of-range inputs in VRSQRTS
11-20 Available immediate ranges in VRSRA (by immediate)
11-21 Available immediate ranges in VSHL (by immediate)
11-22 Available immediate ranges in VSHLL (by immediate)
11-23 Available immediate ranges in VSHR (by immediate)
11-24 Available immediate ranges in VSHRN (by immediate)
11-25 Available immediate ranges in VSRA (by immediate)
11-26 Permitted combinations of parameters for VSTn (multiple n-element structures)
11-27 Permitted combinations of parameters for VSTn (single n-element structure to one lane)
11-28 Operation of doubleword VUZP.8
11-29 Operation of quadword VUZP.32
11-30 Operation of doubleword VZIP.8
11-31 Operation of quadword VZIP.32
12-1 Wireless MMX Technology instructions
12-2 Wireless MMX Technology pseudo-instructions
13-1 List of directives
13-2 OPT directive settings
A-1 Differences between issue J and issue K
A-2 Differences between issue I and issue J
A-3 Differences between issue H and issue I
A-4 Differences between issue G and issue H
A-5 Differences between issue F and issue G
A-6 Differences between issue E and issue F
A-7 Differences between issue D and issue E
A-8 Differences between issue C and issue D
A-9 Differences between issue B and issue C
A-10 Differences between issue A and issue B

Release Information

Document History
Issue Date Confidentiality Change
A May 2010 Non-Confidential ARM Compiler v4.1 Release
B 30 September 2010 Non-Confidential Update 1 for ARM Compiler v4.1
C 28 January 2011 Non-Confidential Update 2 for ARM Compiler v4.1 Patch 3
D 30 April 2011 Non-Confidential ARM Compiler v5.0 Release
E 29 July 2011 Non-Confidential Update 1 for ARM Compiler v5.0
F 30 September 2011 Non-Confidential ARM Compiler v5.01 Release
G 29 February 2012 Non-Confidential Document update 1 for ARM Compiler v5.01 Release
H 27 July 2012 Non-Confidential ARM Compiler v5.02 Release
I 31 January 2013 Non-Confidential ARM Compiler v5.03 Release
J 27 November 2013 Non-Confidential ARM Compiler v5.04 Release
K 10 September 2014 Non-Confidential ARM Compiler v5.05 Release

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