A.1 Revisions for armasm User Guide

The following technical changes have been made to the armasm User Guide.

Table A-1 Differences between issue L and issue M


Topics affected

Removed references to --licretry as the option no longer has an effect. --licretry

Table A-2 Differences between issue K and issue L


Topics affected

Added v7E-M row and added underscores to entries in the XX column where required. 6.4 Built-in variables and constants
Clarified that --cpreproc_opts must contain at least one option. 10.13 --cpreproc_opts=option[,option,…]
Moved the NEON and VFP instructions into separate chapters.
Added the option operand. Removed the label operand from STC{2}.
Clarified that RSC is not available in Thumb code. 11.95 RSC
Removed the distinction between signed and unsigned types from the store instructions.
Removed the label form of the VSTR NEON and VFP instructions.
Added some missing VMOV instructions to the table. 13.1 Summary of VFP instructions
Corrected the availability for SDIV and UDIV instructions.
Removed mention of register Rd and added that LDREXB and LDREXH zero extend the value loaded. 11.48 LDREX
Removed mention of the accumulator and the Ra operand.
Removed the description of --device=name. Chapter 10 Assembler Command-line Options

Table A-3 Differences between issue J and issue K


Topics affected

Added generic notes about supported features in ARM Compiler and code generation between releases. 1.1 About the ARM Compiler toolchain assemblers
Mentioned how to enable and disable alignment checking in ARMv7-M. 6.16 Address alignment
Removed the single quotation marks from the example. 10.13 --cpreproc_opts=option[,option,…]
Corrected the description of Rm in LSL. 11.49 LSL
Added a note about ECC memory to the AREA NOINIT attribute description. 15.6 AREA
Mentioned that there is no 16-bit version of the RBIT instruction in Thumb. 11.87 RBIT
Mentioned the instruction sets supported by the ARMv7 architecture profiles. 2.2 ARM, Thumb, and ThumbEE instruction sets
Included Hyp mode in the diagram and description. 2.8 ARM registers
Added a note to explain the purpose of the example. 4.17 Block copy with LDM and STM
Clarified that LDRD and STRD doubleword data transfers must be eight-byte aligned only in ARMv5TE, or in ARMv6 when SCTLR.U is 0. 15.5 ALIGN
Updated topics for VFPv4.
Added the HVC instruction. 11.37 HVC
Clarified that width+lsb can be equal to 32.
Removed the ThumbEE instructions and removed information specific to ThumbEE instructions from the ARM and Thumb Instructions chapter. Mentioned that information about ThumbEE instructions can be found in the ARM Architecture Reference Manual.
Modified the Address alignment topic. 6.16 Address alignment
Clarified the description of PC-relative expressions. 7.5 Register-relative and PC-relative expressions
Removed the description of --device=list. Chapter 10 Assembler Command-line Options

Table A-4 Differences between issue I and issue J


Topics affected

Added the chapters from the Assembler Reference into the armasm User Guide. The Assembler Reference is no longer being provided as a separate document.

Added the --execute_only command-line option.

10.29 --execute_only

Added the EXECONLY and ZEROALIGN AREA attributes, and mentioned that CODEALIGN is the default for execute-only sections.

15.6 AREA

Changed references to the assembler environment variable from ARMCCn_ASMOPT to ARMCC5_ASMOPT.

--cpu and --fpu options are fully documented
Added topics on via file syntax.
Removed the topics --project, --no_project, --reinitialize_workdir, and --workdir.
Mentioned a difference in behavior between pre-UAL Thumb syntax and UAL syntax for the LDR Rd,= const literal load pseudo-instruction.

Table A-5 Differences between issue H and issue I

Change Topics affected
Where appropriate, changed the term local label to either numeric local label or named local label.
Replaced or removed the term unpredictable. Various instructions
Clarified how the carry flag is set. 5.4 Updates to the condition flags
Where appropriate, changed the terminology that implied that 16-bit Thumb and 32-bit Thumb are separate instruction sets. Various topics
Where appropriate, changed the term processor state to instruction set state.
Clarified the difference between changing the assembler mode and changing the instruction set state. 2.3 Changing between ARM, Thumb, and ThumbEE state

Mentioned that DMB, DSB and ISB cannot be conditional in ARM code.

Corrected the available immediate ranges for VQ{R}SHR{U}N and mentioned the I16, I32, and I64 datatypes.

Mentioned that VFP vector mode and mixed mode are deprecated, for the following VFP instructions: VABS, VADD, VDIV, VMLA, VMLS, VMUL, VNEG, VNMLA, VNMLS, VNMUL, VSQRT, and VSUB.

Chapter 8 NEON Programming
Described the E suffix for the VCMP instruction. 13.4 VCMP, VCMPE
Added the non flag-setting forms to the lists of 16-bit Thumb instructions, for the following instructions: ADC, ADD, AND, ASR, BIC, EOR, LSL, LSR, MOV, MUL, ORR, ROR, RSB, SBC, and SUB. Also mentioned that the corresponding flag-setting forms can only be used outside IT blocks. Chapter 11 ARM and Thumb Instructions
Corrected the examples given for the DCQ and DCQU directives. 15.21 DCQ and DCQU

Table A-6 Differences between issue G and issue H

Change Topics affected

Added a topic about conditional assembly.

6.14 Conditional assembly
Clarified the difference between the --predefine assembler option and the -Dname compiler option. 10.56 --predefine "directive"
Mentioned behavior when using PC or SP with the MRS or MSR instructions.
Added a note about using the ISB instruction in an IT block on ARMv7-M. 11.38 ISB
Separated the V{R}SHR, V{R}SHRN and V{R}SRA instruction descriptions and changed the descriptions of the valid immediate ranges.
Changed the terminology used for ARM architecture versions and added explanatory table footnotes.
Added the CPY and NEG pseudo-instructions.
Expanded the Usage and Example sections for the ENTRY directive. 15.25 ENTRY

Table A-7 Differences between issue F and issue G


Topics affected

Changed the ordering of some operands from vector, scalar, vector to vector, vector, scalar, in the examples of VFP arithmetic instructions.

Where appropriate:

  • Mentioned Thumb-2 technology.

  • Changed 32-bit Thumb to Thumb-2 technology.

Updated the description of --untyped_local_labels.

10.66 --untyped_local_labels

Added the ERET instruction. 11.36 ERET
Mentioned that the MVN instruction exists in a 16-bit Thumb encoding. 11.68 MVN
Added a figure showing the operation of VSHL and updated the figures for VSLI and VSRI.
Added links to the NEON and VFP data types topic from the associated NEON and VFP instructions. Various NEON and VFP instructions
Mentioned that the FUNCTION directive can accept an empty reglist. 15.41 FUNCTION or PROC

Table A-8 Differences between issue E and issue F


Topics affected

Clarified the range of addresses accessible to the ADR instruction and the ADRL pseudo-instruction in ARM state.
Where appropriate:
  • Changed Thumb-2 to 32-bit Thumb.

  • Changed Thumb-2EE to ThumbEE.

Various topics

Changed the minor version component of the built-in variable ARMASM_VERSION from one to two digits.

6.4 Built-in variables and constants

Changed the minor version component of the integer reported by the --version_number option from one to two digits.

10.67 --version_number
Modified the description of --vsn. 10.69 --vsn
Added a note that the --device option is deprecated.
  • --device=list
  • --device=name
Modified the description of --licretry. --licretry
Mentioned a restriction on using LSL in an IT block with a zero value for sh.

11.49 LSL

Table A-9 Differences between issue D and issue E


Topics affected

Added SC300 and SC000 to table of --compatible options.

10.11 --compatible=name

Table A-10 Differences between issue C and issue D


Topics affected

Added note about --use_frame_pointer.

2.9 General-purpose registers

Changed ARMCC41* environment variables to ARMCCnn*. Added a link to the topic Toolchain environment variables.

6.2 Specify command-line options with an environment variable

Added a topic on directives that can be omitted in pass 2 and added a link to this topic from How the assembler works.

1.4 Directives that can be omitted in pass 2 of the assembler

Added that all instructions must appear in both passes.

1.3 How the assembler works

In the summary table, changed instruction mnemonics from:





12.1 Summary of NEON instructions

Added GBLA count to the example.

15.68 WHILE and WEND

Changed FPv4_SP to FPv4-SP.

10.34 --fpu=name

Made changes to ALinknames for MRS, MSR, SEV, SYS, and NOP instructions.

Table A-11 Differences between issue B and issue C


Topics affected

Added topic on 2 pass assembler diagnostics.

6.13 Two pass assembler diagnostics

Added topic on How the assembler works.

1.3 How the assembler works

Changed the restrictions to say that Rt must be even-numbered only in LDREXD and STREXD instructions.

Mentioned the additional cases where SP and PC are deprecated.

Mentioned that deprecation of SP and PC is only in ARMv6T2 and above.

Various instructions

Added example of inconsistent use of MAP and FIELD directives.

15.29 FIELD

Changed --cpu PXA270 to --device PXA270.

14.1 About Wireless MMX Technology instructions

Table A-12 Differences between issue A and issue B


Topics affected

Split the General-purpose registers topic into two. The second topic is called Register accesses.

Mentioned that PC is not considered to be a general-purpose register and that the instruction topics describe when SP and PC can be used.

2.9 General-purpose registers

Mentioned that the use of PC in reglist in 32-bit Thumb instructions is for LDM and POP only.

Added a note that ARM instructions are deprecated if reglist contains SP or PC (STM and PUSH), or both PC and LR (LDM and POP).

Added a topic on Instruction and directive relocations.

4.24 Instruction and directive relocations

Added a topic on Thumb code size diagnostics.

6.10 Thumb code size diagnostics

Added a topic on ARM and Thumb instruction portability diagnostics.

6.11 ARM and Thumb instruction portability diagnostics

Added a link to Thumb code size diagnostics.

6.17 Instruction width selection in Thumb

Added that symbols beginning with $v must be avoided.

7.1 Symbol naming rules

Removed | as an alias for :OR:

7.24 Addition, subtraction, and logical operators

Clarified that NEON is optionally available on ARMv7-A and ARMv7-R but not on ARMv7E-M. Clarified that ARMv7E-M adds only the VFP single-precision floating-point instructions.

8.1 Architecture support for NEON

Added a new topic on how to input assembly code using stdin.

6.3 Using stdin to input source code to the assembler

Added the options --execstack and --no_execstack.

10.28 --execstack, --no_execstack

Updated the description of --cpu=name.

10.15 --cpu=name

Added the option --fpmode=none.

10.32 --fpmode=model

Updated the description of --show_cmdline.

10.60 --show_cmdline

Updated the instruction summary table and footnotes with ARMv7E-M.

11.1 ARM and Thumb instruction summary

Replaced "profile" with "architecture" when referring to ARMv6-M, ARMv7-M, ARMv7-R, and ARMv7-A in the instruction summary table and in the architecture sections of the instruction descriptions.

11.1 ARM and Thumb instruction summary

Mentioned register-controlled shift in the description of Operand2.

11.5 Syntax of Operand2 as a register with optional shift

Added register restrictions to ADR (PC-relative).

11.11 ADR (PC-relative)

Added register restrictions and deprecation information in LDR and STR (immediate offset).

Identified the ARM only instruction syntaxes in LDR and STR (register offset).

Added register restrictions and deprecation information, use of SP, and use of PC in LDR and STR (register offset).

Noted that PC-relative STR is available but deprecated.

11.43 LDR (PC-relative)

Added information about deprecation and use of SP in LDR (PC-relative).

11.43 LDR (PC-relative)

In Restrictions on reglist in ARM instructions, added that reglist containing both PC and LR in ARM LDM is deprecated.

11.41 LDM

Added Restrictions of reglist in ARM instructions.

11.75 POP

Added register restriction for Rn and moved the statement "Rm must not be PC" to this section.

11.74 PLD, PLDW, and PLI

Added restrictions on reglist in LDM and STM.

Added the statement "must not be PC" for each of the registers in the syntax.

11.143 SWP and SWPB

Mentioned SUBS pc, lr in Use of PC and SP in ARM instructions.

11.10 ADD

Removed the caution against the use of the S suffix when using PC as Rd in User or System mode.

11.10 ADD

Mentioned the deprecated instructions that use PC.

11.10 ADD

Added more syntaxes that are only present in ARM code and described the additional items in the syntax.

11.141 SUBS pc, lr

Documented the valid forms of the SUBS instruction in ARM and Thumb, and added the caution to not use these instructions in User or System mode.

11.141 SUBS pc, lr

Mentioned SUBS pc, lr in Use of PC and SP in ARM instructions.

11.14 AND

Removed the caution against the use of the S suffix when using PC as Rd in User or System mode.

11.14 AND

Added Register restrictions section to say Rn cannot be PC in instructions that write back to Rn.

11.40 LDC and LDC2

Mentioned that Rt cannot be PC.

11.52 MCR and MCR2

Mentioned that Rm cannot be PC.

11.66 MSR (general-purpose register to PSR)

Mentioned SUBS pc, lr in Use of PC and SP in ARM MOV.

11.57 MOV

Removed the caution against the use of the S suffix when using PC as Rd in User or System mode.

11.57 MOV

Mentioned the deprecated instructions that use PC.

11.57 MOV

Mentioned that SP is not permitted in Thumb TST and TEQ instructions, and is deprecated in ARM TST and TEQ instructions.

Added that SEL is available in ARMv7E-M.

11.102 SEL

Added that Rn must be different from Rd in MUL and MLA before ARMv6.

Added that Rn must be different from RdLo and RdHi before ARMv6.

11.167 UMULL

Added that the Thumb instructions are available in ARMv7E-M.

DBG is available in ARMv6K and above in ARM, and in ARMv6T2 and above in Thumb. Also mentioned that DBG executes as NOP in ARMv6K and ARMv6T2.

11.32 DBG

Added figures for the operation of VSLI and VSRI.

Added tables showing the register state before and after operation of VUZP and VZIP.

Added that n can be a defined relocation name and added a related example in the examples section.

15.57 RELOC

Added a note for a macro workaround when using |.

15.51 MACRO and MEND

Clarified the message to say that error generation is during assembly rather than second pass of the assembly.


Added the ALIAS directive.

15.4 ALIAS

Clarified that n is any integer, and described the examples in the examples sections.

15.5 ALIGN

Clarified the description of COMGROUP and GROUP.

15.6 AREA

Added note about R_ARM_TARGET1.

15.6 AREA

Added link to 8 Byte Stack Alignment.


Added /hardfp and /softfp values to the --apcs option and added a link to the --apcs compiler option.

10.3 --apcs=qualifier…qualifier

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