2.18 Current Program Status Register

The Current Program Status Register (CPSR) holds the same program status flags as the APSR, and some additional information.

The CPSR holds:

  • The APSR flags.

  • The processor mode.

  • The interrupt disable flags.

  • The instruction set state (ARM, Thumb, ThumbEE, or Jazelle®).

  • The endianness state (on ARMv4T and later).

  • The execution state bits for the IT block (on ARMv6T2 and later).

The execution state bits control conditional execution in the IT block.

Only the APSR flags are accessible in all modes. ARM deprecates using an MSR instruction to change the endianness bit (E) of the CPSR, in any mode. SETEND is the preferred instruction to write to the E bit.

The execution state bits for the IT block (IT[1:0]), Jazelle bit (J), and Thumb bit (T) can be accessed by MRS only in Debug state.

Note:

The CPSR is not present in ARMv6-M and ARMv7-M processors.
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